AN10061 Inphi PAM4 Performance when Driving Shared Reference Clocks

The Inphi Polaris and Vega 400G PAM4 DSP families [1] have dual die variants. In some cases, the reference clock (REFCLK) input for each die is brought out separately. In other cases, the reference clocks are connected together on the substrate (in the package) and only one reference clock input is brought out to the device pins. For all these dual-die variants, it is preferable to use a single REFCLK source to minimize space, cost, and power in the end application. The Inphi and SiTime applications teams have prepared and tested two reference clock configurations:

  1. A SiTime Elite Platform™ SiT9365 156.25 MHz oscillator [2] as a common reference clock for both dies – this is the recommended configuration
  2. A quartz clock generator on the Inphi Helios Evaluation Board (EVB) to drive the reference clock inputs of each die individually – this is the default board configuration The test for both configurations was conducted on the Inphi Helios Evaluation Platform at the Inphi lab.

The purpose is to validate that the SiT9365 LVPECL differential clock can simultaneously drive two reference clock inputs of the Inphi PAM4 DSP while achieving optimum performance. All testing was done on the Inphi TX outputs at 28.125 Gbaud with PRBS7 pattern in Line PRBS Mode.


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