Ultra Low Jitter, Quad PLL, Programmable Frequency, 12-output Clock Generator
LoginThe SiT95211 offers programmable quad fractional frequency generation and translation with flexible input to output frequency translation options. Ultra high jitter performance DPLL supports up to 4 differential or single-ended input clocks that are common for all the 4 fractional PLLs and provides 12 differential output clocks. The clock outputs can be derived from any of the 4 PLLs in a fully flexible manner. This device is fully programmable with the I2C/SPI interface or an on-chip one-time programmable non-volatile memory for factory pre-programmed devices.
- Lower phase noise minimizes bit error rate and increases design margin in 56G/112G PAM4 I/O systems
- Better signal integrity increases design margin and leads to faster time to market
- Higher clock tree integration reduces system BOM and increases overall reliability
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| "Specs" | "Value" |
|---|---|
| Operating Temperature Range (°C) | -40 to 85 |
| Package Type (mm²) | 9x9 mm, 64-pin QFN |
| Number of Inputs | 4 |
| Number of Outputs | 12 |
| Input Type | LVCMOS, LVDS, LVPECL, CML |
| Input Frequency Range | 200 kHz to 2.1 GHz (Differential) |
| Output Type | LVPECL, CML, HCSL, LVDS, LVCMOS |
| Output Frequency Range | 0.5 Hz to 2.94912 GHz (Differential) |
| Number of PLL/Clock Domains | 4 PLL |
| Phase Jitter (rms) | 85 fs typ.; 70 fs typ. (with MEMS oscillator) |
| Repeatable Input-Output Delay | ±225 ps |
| Frequency Control DCO | 0.001 ppt (all outputs) |
| Phase Control DCO | <1 ps (all outputs) |
| Internal ZDB Mode | <0.5 ns Input to Output delay variation |
| Programmability | NVM OTP, External EEPROM, Partial autonomous, SPI/I2C |
| Features | Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V |
| Availability | Production |
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64-pin 9x9 mm QFN Clock Generators - Network Synchronizers - Jitter Cleaners package
- Best in Class 85 fs / 70 fs integrated jitter for Quad PLL
- JESD204B/C Support for data converter clocks
- External EEPROM Support and on Chip OTP
- Frequency DCO (0.001ppt) and Phase control DCOs (< 1ps resolution)
- Internal ZDB on all PLLs with < +/- 500 ps input to output delay across temp
- Independent VDDO (3.3 / 2.5 / 1.8 V)
- Outputs can be phase aligned on independent sync pulse
- Ethernet
- Optical Transport Network (OTN) Clocking for Framers, Mappers & Processors
- Microwave Backhaul
- 100G / 200G / 400G / 800G Ethernet
- Wireless Networks
- Small Cells
- Storage, Servers & Datacenters
- SONET/SDH Stratum 3
- Test & Measurement
- Broadcast Video
SiT95211 Evaluation Board HW User Manual – Configure and evaluate device performance
Setup SiTGUI 3.6 – Download software .exe file
| Resource Name | Resource Type | Date | Format | Size |
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