Clock Buffers
SiTime offers a range of high-performance clock buffers that support a wide range of frequencies, five standard input types, and up to 10 single-ended or 20 differential outputs. With low additive jitter and low output-to-output skew, these buffers are ideal for jitter-sensitive applications. Their low power consumption makes them ideal for battery-driven and high-density applications.
High-Performance Buffers
Fanout clock buffers for low jitter, high frequency clock/data distribution.
- Output frequency up to 2.1 GHz
- Ultra-low output-to-output skew, as low as 30 ps (typical)
- Low additive jitter, 50 to 55 fs rms
- Low propagation delay, as low as <1.6 ns
- Wide voltage operation for design compatibility
- Output enable (OE) signal for output synchronization (SiT92112, SiT92114, SiT92216)
- Level translation
| Device | Datasheet | Buy Now | Number of Inputs | Number of Outputs | Max. Output Frequency | Max. Output Skew | Additive Phase Jitter(rms) | Package(mm) |
|---|---|---|---|---|---|---|---|---|
| SiT92110 |
|
1 | 10 Single Ended | 250 MHz | 30 ps | 50 fs | 5x5 mm, 32-pin QFN | |
| SiT92112 |
|
1 | 2 Single Ended | 200 MHz | 50 ps | 50 fs | 2x2 mm, 8-pin DFN | |
| SiT92113 |
|
1 | 5 Single Ended | 250 MHz | 30 ps | 50 fs | 4x4 mm, 24-pin QFN | |
| SiT92114 |
|
1 | 4 Single Ended | 200 MHz | 50 ps | 50 fs | 2.0 x 2.0 8-pin DFN 3.0 x 4.4 8-pin TSSOP | |
| SiT92206 |
|
3 | 6 Differential | 2.1 GHz | 30 ps | 55 fs (typ.) | 6x6 mm, 36-pin QFN | |
| SiT92208 |
|
3 | 8 Differential | 2.1 GHz | 30 ps | 55 fs (typ.) | 6x6 mm, 40-pin QFN | |
| SiT92211 |
|
1 | 10 Differential | 2.1 GHz | 30 ps | 55 fs | 7x7 mm, 48-pin QFN | |
| SiT92216 |
|
1 | 4 Differential 1 Single Ended | 2.1 GHz | 30 ps | 50 fs | 5x5 mm, 32-pin QFN |
PCIe Buffers
Fanout buffers that meet or exceed all the performance requirements of the Intel DB2000QL specification designed for PCI-Express Gen 1-6 or QP/UPI applications.
- Ultra-low output-to-output skew, <50 ps (typical)
- Ultra-low additive jitter, 8 fs rms
- Low propagation delay
- Output enable (OE) signal for output synchronization
- Level translation
| Device | Datasheet | Buy Now | Number of Inputs | Number of Outputs | Max. Output Frequency | Max. Output Skew | Additive Phase Jitter(rms) | Package(mm) |
|---|---|---|---|---|---|---|---|---|
| SiT92310 |
|
1 | 20 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 10x10 mm, 72-pin QFN | |
| SiT92313 |
|
1 | 8 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 6x6 mm, 48-pin LGA | |
| SiT92314 |
|
1 | 4 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 5x5 mm, 32-pin VQFN | |
| SiT92315 |
|
1 | 20 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 6x6 mm, 80-pin LGA | |
| SiT92316 |
|
1 | 6 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 5x5 mm, 40-pin VQFN | |
| SiT92317 |
|
1 | 6 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 5x5 mm, 40-pin VQFN | |
| SiT92318 |
|
1 | 8 Differential | 400 MHz | 50 ps | 8 fs (PCIe Gen6 @100 MHz) | 6x6 mm, 48-pin VQFN |
Automotive Buffers
Automotive grade 1, AEC-Q100-qualified, high-performance fanout clock buffers.
- Automotive Grade -40°C to 125°C operation
- Ultra-low output-to-output skew, <50 ps (typical)
- Low additive jitter, 50 fs rms
- Low propagation delay
- Wide voltage operation for design compatibility
- Output enable (OE) signal for output synchronization
- Level translation
| Device | Datasheet | Buy Now | Number of Inputs | Number of Outputs | Max. Output Frequency | Max. Output Skew | Additive Phase Jitter(rms) | Package(mm) |
|---|---|---|---|---|---|---|---|---|
| SiT92182 |
|
1 | 2 Single Ended | 200 MHz | 50 ps | 50 fs | 2x2 mm, 8-pin DFN | |
| SiT92184 |
|
1 | 4 Single Ended | 200 MHz | 50 ps | 50 fs | 2x2 mm, 8-pin DFN |