The SiT92216 is a low-jitter fanout clock buffer with 4 differential outputs and 1 LVCMOS outputs. It is ideal for low jitter, high frequency clock/data distribution. The low impedance LVCMOS outputs are designed to drive 50 Ω series or parallel terminated transmission lines.
The buffer can use a clock input from primary or secondary clock sources, either single ended or fully differential. The selected clock is distributed to 4 differential and 1 LVCMOS output drivers.
The SiT92216 operates from a 3.3 V/2.5 V core supply and 3.3 V/2.5 V output supply. The HCSL and LVCMOS output drivers can operate at 1.8 V. The core supply and output supply are independent of each other and no supply sequencing is required.

"Specs" | "Value" |
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Operating Temperature Range (°C) | -40 to 85 |
Package Type (mm²) | 5x5 mm, 32-pin QFN |
Buffer Type | Fanout |
Number of Inputs | 1 |
Number of Outputs | 4 Differential, 1 Single Ended |
Input Type | LVPECL, LVDS, HCSL, LVCMOS |
Input Frequency Range | 0 Hz to 2.1 GHz |
Output Type | LVPECL, LVDS, HCSL, LVCMOS |
Output Frequency Range | 0 Hz to 2.1 GHz |
Additive Phase Jitter (rms) | 50 fs |
Propagation Delay, Typical | 0.8 ns to 1.4 ns |
Output-Output Skew, Typical | 30 ps |
PCIe Support | Gen 1 to Gen 5 |
Output Enable | Yes |
Availability | Production |
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5x5 mm, 32-pin QFN Clock Buffer package
- Level translation with core supply voltage of 3.3 V/2.5 V and 3.3 V/2.5 V output supply for differential output drivers.
- 1.8 V output supply support for LVCMOS and HCSL driver.
- The inputs are selected by programming input select pins of SiT92216. The input clock receiver in SiT92216 can accept LVPECL, LVDS, LVCMOS, SSTL, HCSL and OSC waveforms.
- Input frequencies are supported from DC to 2100 MHz are supported on primary and secondary inputs.
- Supports PCIe Gen 1 to Gen 5.

- Ethernet
- 5G Infrastructure
- Wireless Base Stations
- Small Cells
SiT92216 Evaluation Board HW User Manual – Configure and evaluate device performance
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