1.8 V to 3.3 V, 4 LVCMOS Output, Ultra-Low-Jitter, Fanout Clock Buffer

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The SiT92114 is a high-performance LVCMOS fanout clock buffer with low additive phase jitter of 50 fs RMS.

The SiT92114 supports a synchronous glitch-free output enable (OE) function to eliminate potential intermediate incorrect output clock cycles when enabling or disabling outputs. It can operate from a 1.8 V to 3.3 V supply.


2x2 mm, 8-pin DFN Clock Buffer package
"Specs" "Value"
Operating Temperature Range (°C) -40 to 85
Package Type (mm²) 2x2 mm, 8-pin DFN
Buffer Type Fanout
Number of Inputs 1
Number of Outputs 4 Single Ended
Input Type LVCMOS
Input Frequency Range 0 Hz to 200 MHz
Output Type LVCMOS
Output Frequency Range 0 Hz to 200 MHz
Additive Phase Jitter (rms) 50 fs
Propagation Delay, Typical 1.0 ns
Output-Output Skew, Typical 50 ps
Output Enable Yes
Availability Production
  • 3.3 V tolerant input clock.
  • Integrated serial termination for 50 Ω channel.
SiT92114 Functional Overview
  • Wireless Base Stations
  • 5G Infrastructure
  • Telecom Equipment
  • Computer Servers
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