Jitter is the timing variations of a set of signal edges from their ideal values. Jitters in clock signals are typically caused by noise or other disturbances in the system. Contributing factors include thermal noise, power supply variations, loading conditions, device noise, and interference coupled from nearby circuits.
Jitter can be measured in a number of ways; the following are the major types of jitter:
- Period Jitter
- Cycle to Cycle Period Jitter
- Long Term Jitter
- Phase Jitter
- Time Interval Error (TIE)
Period jitter is the deviation in cycle time of a clock signal with respect to the ideal period over a number of randomly selected cycles. If we were given a number of individual clock periods, we can measure each one and calculate the average clock period as well as the standard deviation and the peak-to-peak value. The standard deviation and the peak-to-peak value are frequently referred to as the RMS value and the Pk-Pk period jitter, respectively.
Many publications defined period jitter as the difference between a measured clock period and the ideal period. In real world applications, it is often difficult to quantify the ideal period. If we observe the output from an oscillator set to 100 MHz using an oscilloscope, the average measured clock period may be 9.998 ns instead of 10 ns. So it is usually more practical to treat the average period as the ideal period.
Period jitter is useful in calculating timing margins in digital systems. Consider a microprocessor-based system in which the processor requires 1 ns of data setup before clock rise. If the period jitter of the clock is -1.5 ns, then the rising edge of the clock could occur before the data is valid. Hence the microprocessor will be presented with incorrect data. This example is illustrated in Figure 1.
Similarly, if another microprocessor has a data hold time requirement of 2 ns but now the clock jitter is +1.5 ns, then the data hold time is effectively reduced to 0.5 ns. Once again, the microprocessor will see incorrect data. This situation is illustrated in Figure 2.
Because the period jitter from a clock is random in nature with Gaussian distribution, it can be completely expressed in terms of its Root Mean Square (RMS) value in pico-seconds (ps). However, the peak-to-peak value is more relevant in calculating setup and hold time budgets. To convert the RMS jitter to peak-to-peak (Pk-Pk) jitter for a sample size of 10,000, the reader can use the following equation:
𝑃𝑒𝑎𝑘‒ 𝑡𝑜‒ 𝑝𝑒𝑎𝑘 𝑝𝑒𝑟𝑖𝑜𝑑 𝑗𝑖𝑡𝑡𝑒𝑟 = ±3.719 𝑥 (𝑅𝑀𝑆 𝑗𝑖𝑡𝑡𝑒𝑟) Equation 1
For example, if the RMS jitter is 3 ps, the peak to peak jitter is ±11.16 ps.
Equation 1 is derived from the Gaussian probability density function (PDF) table. For instance, if the sample size is 100, 99 of those samples will fall within ±2.327σ from the mean value of the distribution, only 1 sample, on average, will fall outside that region. SiTime measures the RMS period jitter over a sample size of 10,000 as specified by the JEDEC standard.
Period Jitter is defined in JEDEC Standard 65B as the deviation in cycle time of a signal with respect to the ideal period over a number of randomly selected cycles. The JEDEC standard further specified that period jitter should be measured over a sample of 10,000 cycles. SiTime recommends measuring period jitter using the following procedure:
The standard deviation (σ) or RMS value computed from a measurement of 10,000 random samples(step 4) is quite accurate. The error in the RMS value can be calculated using the following equation:
where σn is the RMS (or sigma) of the collected sample and N is the sample size. For a sample size of 10,000, ErrorRMS is 0.0071σn. This error is random and it follows the Gaussian distribution. The worst-case measurement error is typically computed as ±3 ErrorRMS.
For example, if the RMS value computed from 10,000 random samples is 10 ps, then the ErrorRMS will be 0.071 ps and virtually all the RMS values of this measurement will still fall within a narrow range of 10 ± 0.213 ps. In practical applications, the RMS errors in a sample set of 10,000 are small enough to be ignored.
While an accurate RMS value can be computed from a random 10000-sample set, the peak-to-peak value is more difficult to measure. Due to the random nature of period jitter, the larger the sample size, the higher is the probability of picking up data points at the far ends of the distribution curve. In other words, the peak-to-peak value diverges instead of converging as more samples are collected. That is the reason why we added an extra step, step 5 to produce a more consistent and repeatable peak-to-peak measurement.
Each measurement of 10,000 random samples (step 4) produces one standard deviation value and one peak-to-peak value. By randomly repeating this process 25 times, we could collect a good set of data points from which we can calculate the average peak-to-peak value with a high degree of accuracy. We can also compute the average RMS value from this data, but it will be very close to the RMS value derived from each individual run.
Figure 3 is the period jitter histogram and period trend of a 3.3V TCXO oscillator running at 24 MHz captured by DSA90804A Infiniium High Performance Oscilloscope. It represents one set of RMS value measured from 10,000 samples (step 4).
Cycle to cycle (C2C) jitter is defined in JEDEC Standard 65B as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. The JEDEC standard further specified that each sample size should be greater than or equal to 1,000. Please note that cycle to cycle jitter only involves the difference in period between 2 consecutive cycles, there is no reference to an ideal cycle.
Cycle to cycle jitter is typically reported as a peak value in ps which defines the maximum deviation between the rising edges of any two consecutive clocks. This type of jitter specification is commonly used to illustrate the stability of spread spectrum clocks because the period jitter is more sensitive to the frequency spreading feature while C2C jitter is not. Cycle to cycle jitter is sometimes expressed as a RMS value in ps as well.
SiTime recommends measuring cycle to cycle jitter using the following procedure:
Similar to the peak-to-peak period jitter, the peak value of the cycle to cycle jitter also diverges instead of converging as more samples are taken. Step 6 in the procedure is added to obtain the average peak C2C jitter from 25 sample sets.
Figure 4 is an example of the cycle to cycle jitter histogram and period trend. In this case, the peak cycle to cycle jitter is 10.03 ps (the bigger of the two numbers: -10.03 ps and 7.79 ps expressed in the absolute form).
Long-term jitter measures the change in a clock’s output from the ideal position, over several consecutive cycles. The actual number of cycles used in the measurement is application dependent. Long-term jitter is different from period jitter and cycle-to-cycle jitter because it represents the cumulative effect of jitter on a continuous stream of clock cycles over a long time interval. That is why long-term jitter is sometimes referred to as the accumulated jitter. Long-term jitter is typically useful in graphics/video displays and long-range telemetry applications such as range finders.
SiTime recommends measuring long-term jitter using the following method; in this example, we measure the long-term jitter over 10,000 clocks.
Once again, step 5 is needed to overcome the un-bounded nature of the peak-to-peak value.
Phase noise is usually described as either a set of noise values at different frequency offsets (e.g., -60 dBc/Hz at 20 kHz and -95 dBc/Hz at 10 MHz), or as a continuous noise plot over a range of frequencies. Phase jitter is the integration of phase noises over a certain spectrum and expressed in seconds.
In a square wave, most of the energies are located at the carrier frequency. However, some signal energies are “leaked-out” over a range of frequencies on both sides of the carrier. Phase jitter is the amount of phase noise energy contained between two offset frequencies relative to the carrier (fc). Figure 6 is an unfiltered phase noise plot and the shaded areas represent the phase jitter between frequencies f1 and f2.
The RMS phase jitter between f1 and f2 is defined by Equation 3.
In communication applications, the bandpass filter effect of the combined TX PLL and RX PLL is applied to the raw phase noise data before the final RMS phase jitter value is calculated. The following are common applications and the bandwidth (corner frequencies) of their associated filters:
If the filter function is H(f), then the filtered RMS phase jitter can be calculated using Equation 4.
Time Interval Error (TIE) of an edge is the time deviation of that edge from its ideal position measured from a reference point. In effect, TIE is the discrete time domain representation of phase noise expressed in seconds or pico-seconds. Figure 7 illustrates the basic concept of TIE. The ideal signal is often a signal created in software from an average estimate of the signal period.
A clock waveform is shown at the top of Figure 8. The red pulses are perfectly timed clock cycles exactly 1000 ps in duration. The pulses in black are clock cycles with jitter. The trailing edges of these clock pulses have been removed to enhance the presentation. At the beginning of the sequence, both the red and black clocks are aligned to each other. Because of the jitter, the black clock edges will start shifting in time, sometimes occurring before the red clock edge and sometimes after.
The plot labeled “Clock Period” represents the measured black clock periods over time. In this example, the black clock periods are either 990 ps or 1010 ps. The “Period Change” plot depicts each cycle’s change from the previous cycle. This graph remains flat as long as the period between two consecutive black clocks stays the same. However, it will register a change whenever a period difference is detected.
For example, the period of the first 4 clock cycles are constant at 990 ps, so the “Period Change” plot is flat; but when the period of the fifth clock is lengthened from 990 ps to 1010 ps, the plot reports this change by jumping to the +20 ps position. In other words, this plot identifies the period changes shown in the “Clock Period” plot.
The “Time Interval Error” (TIE) plot documents the accumulated error between the ideal edge (red clock) and the actual edge (black clock). In this example, the TIE plot begins by moving towards the negative direction because the first 4 clocks are each 10 ns shorter than the ideal period. After accumulating -40 ps in jitter error, the plot changes direction at the fifth clock and heads towards the positive direction because the fifth clock period is 10 ps longer than the ideal period.
TIE measurements are especially useful when examining the behavior of transmitted data streams, where the reference clock is typically recovered from the data signal using a Clock/Data Recovery (CDR) circuit. A large TIE value may indicate that the PLL in the CDR is too slow in responding to the data stream’s changing bit rate.
The most common instrument used in measuring clock jitter is the real time digital oscilloscope (scope). This section contains general scope setup guidelines to yield better jitter measurement accuracy.
The digital scope uses an internal time base to sample its inputs at regular intervals. The sampling rate can range from 1 Gsps (giga-samples-per-second) to 40 Gsps for the high-end units. Figure 9 illustrates how the digital scope samples and displays a signal presented to its inputs. The arrows at the bottom of the figure represent the sampling points, the solid line is the actual signal, and the dots are the sampled values. The signal displayed by the scope (represented by the dotted line) is the best-fit curve across the sampled points.
The reader may notice that the sampled values do not always match that of the actual signal. These discrepancies are caused by quantization errors in the scope. Most of these errors are inherent in the design/cost tradeoffs of the scope but proper scope setup can mitigate some of the inaccuracies. In the following sections, we will explore the main causes of these errors and recommend steps to reduce their impact on jitter measurements.
The inputs to a digital scope passed through an analog amplifier before they are digitized by the Analog to Digital Converter (ADC). The noise produced by this amplifier is proportional to the input bandwidth of the scope: the wider the bandwidth, the higher the noise. However, reducing the bandwidth too much will affect the rising and fall time of the sampled signal, thus introducing significant errors to the jitter measurement.
The general equation describing the relationship between rise time/fall time and the bandwidth of the signal edge is:
where the rise time (or fall time) is measured between the 20% and the 80% points of the signal edge. SiTime recommends setting the scope bandwidth to 3 times the bandwidth of the signal. In some scopes, the bandwidth can be set only if the maximum sampling rate is selected. In other scopes, the bandwidth may not be selectable at all.
Quantization error is the difference between the sampled value and the actual value of the signal at the sampling point. This error is shown in Figure 9. A portion of this error in a scope is caused by the vertical gain setting of the display. If the vertical gain is set to small value, the scope may not utilize the full resolution of its internal ADC.
SiTime recommends adjusting the vertical gain control of the scope until the signal fills the entire height of the display. In some scopes, turning the vertical gain up an additional notch so that a small portion of the signal is clipped at both the top and bottom of the display could further reduce the quantization error. This benefit is achieved because the higher vertical gain setting may cause the scope to utilize an extra bit in the ADC to digitize the signal. However, this feature is scope dependent, so please consult your scope manual.
Some of the quantization noise described in the previous section is caused by insufficient sampling points along the horizontal axis. SiTime recommends having at least 3 sampling points falling between the 20% and 80% points of a rising or falling edge. This recommendation translates into a minimum sampling rate requirement for the scope. For example, if rise time (20% - 80%) of a signal is 1 ns and 4 sampling points are needed within this time frame, then the scope must have a sampling rate better than 4 Gsps. If your scope has a higher sampling rate than the minimum requirement specified above, select the highest sampling setting.
The sampling points in a digital scope are generated by an internal time base. As a clock source, the time base has its own jitter characteristics and it will contribute to the jitter measurement error of a signal. Generally speaking, time base jitter should be kept below 25% of the of the expected signal jitter to support jitter measurement with better than 3% accuracy. SiTime recommends using the best scope available in your laboratory to perform jitter measurements because higher end units tend to have better time base circuits with lower jitter.
Method A
Method B (the JEDEC method)
Method A
Method B
This application note serves two purposes. First, it describes the common types of jitter that the reader may encounter in today’s high speed systems. Second, it provides the procedures to capture the various types of jitters using a real time digital oscilloscope. Phase noise and consequently phase jitter measurement technique is described in the AN10062 Phase Noise Measurement Guide for Oscillators.
Table 2. Revision History
Version |
Release Date |
Change Summary |
1.11 |
05/14/2009 |
Original doc |
1.2 |
01/22/2014 |
Edited Equation 1 (Pk-Pk period jitter) |
1.21 |
04/26/2019 |
Edited Equation 1 (Pk-Pk period jitter) Updated Period jitter and Cycle to cycle jitter (Figure 3 and Figure 4) Added AN10062 reference Updated logo and company address, other page layout & editorial changes |