Host Bus Adapter

Host Bus Adapter

Host bus adapters (HBA) need an accurate and robust timing source to meet the desired high-bandwidth requirements. SiTime MEMS timing technology provides an extremely stable clock reference that has superior performance under harsh environmental conditions.

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SiTime MEMS Timing Benefits

Complete MEMS clock tree

Clock generators

Low jitter differential oscillators

More robust in real-world conditions

4x better dF/dT for accurate clocking

Resistant to airflow and heat

Immunity to power supply noise

Thin profile, easy to use

No cover or shielding

≤1 mm thin to fit back of a card

HBA platforms provide high-speed connections to memory and IO sub-systems for datacenter servers. Solid state disk-drives (SSD) are the most common form of high-speed, high-capacity memory devices used in datacenter applications. Host bus adapter platforms offer a scalable path to managing data storage capacity in server clusters deployed. HBA platforms decouple the compute servers from memory disk drive clusters and typically, a single HBA platform can service multiple compute servers.

Host Bus Adapter (HBA) Block Diagram

Host Bus Adapter (HBA) Block Diagramsitime.comSiT9121xSiT950x

The key technology trends driving HBA platform designs are distributed compute architectures, high density server clusters, high-capacity memory disk drivers and high-speed interfaces. All of these deliver high performance measured in memory and IO transfer rates.

High performance often translates to high power consumption and thermal management challenges. NVM Express (NVMe) technology based memory drives are also susceptible to failures under vibration. SiTime MEMS based oscillators and clock generators are ideally suited to deliver extremely stable, high frequency and low jitter clocks that are impervious to harsh environmental conditions.

MEMS Timing for Host Bus Adapters

Devices Key Features Key Values
Differential Oscillators
SiT9375  25 to 644.5 MHz, 70 fs Integrated Phase Jitter [1]
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SiT9501  25 to 644.5 MHz, 150 fs Integrated Phase Jitter [1]
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  • ±20 ppm to ±50 ppm frequency stability
  • LVPECL, LVDS, HCSL
  • 1.8 V to 3.3 V
  • -40°C to 105°C
  • 2.0 x 1.6 mm, 2.5 x 2.0 mm, 3.2 x 2.5 mm packages
  • Meets demanding jitter requirements
  • Small PCB footprint, easier layout
  • Easy design due to flexibility
  • MEMS reliability
Clock Generator
SiT91211 [2]  1 to 750 MHz, 200 fs Integrated Phase Jitter [1]
SiT91213 [2]  1 to 750 MHz, 90 fs Integrated Phase Jitter [1]
  • 4 differential output clocks
  • ±20 ppm frequency stability
  • LVDS, LVPECL, LPHCSL
  • 0.01 ps/mV PSRR
  • -40°C to 105°C
  • 4 mm x 4 mm package
  • Simplifies clock tree design with multiple low jitter clocks
  • Programmable clocks add flexibility to complex clocking architectures
  • Better frequency stability and noise immunity in harsh environments
  • Small PCB footprint, compact layout

[1] 12 kHz to 20 MHz integration range; [2]  Contact SiTime for availability

MEMS Timing Outperforms Quartz

Ultra-Low Phase Noise, 156.25 MHz

Smallest Packages

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SiTime – Ultra-Low Phase Noise, 156.25 MHz
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SiTime – Smallest Packages
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