The rise and fall times of the clock signal are important parameters for digital systems. In general, clock logic circuits benefit from fast clock rise and fall times, since these minimize the impact of power supply jitter. On the other hand, a slower slew rate on clock edge transitions may reduce electromagnetic interference (EMI) emissions from the printed circuit board. The rise and fall times of an oscillator output driving a capacitive load depend on 1) the maximum drive strength of the oscillator output stage, and 2) the output load capacitance. The rise and fall times of SiTime oscillators with single-ended CMOS output are typically specified in the datasheet for a load capacitance of 15 pF. However, SiTime oscillators are designed to offer a wide range of drive strength options. This allows designers to optimize the rise/fall times for their specific applications.