Clock signals with fast edges see traces on Printed Circuit Boards (PCB) as transmission lines rather than simple wire connections. If the length of PCB trace exceeds certain limit it requires matching of the trace impedance to one or both of the source and load impedances. Impedance mismatch causes signal reflections travelling back and forth the transmission line causing signal distortions such as ringing, overshoots, and undershoots. This application note provides guidelines for proper termination of single-ended traces driven primarily with LVCMOS outputs. This document discusses single-load as well as multiple-load scenarios.