Resistant to power supply noise

Resistant to power supply noise

Want to simplify power supply issues and ensure signal integrity?
SiTime timing solutions can help.

SiTime MEMS oscillators integrate multiple on-chip voltage regulators to filter power supply noise, minimizing the need for an external dedicated LDO and improving signal integrity. Our oscillators offer higher robustness with power-supply-induced jitter sensitivity as low as 0.01 ps/mV.

Check out our differential oscillators with low jitter sensitivity

Device Frequency Power Supply Induced Jitter Sensitivity Phase Jitter (rms) Frequency Stability (ppm) Temperature Range (°C) Package Size (mm)
SiT9501 14 standard frequencies 0.01 ps/mV 70 fs ±20, ±25, ±30, ±50 Up to -40 to +105 2.0x1.6, 2.5x2.0, 3.2x2.5
SiT9375 31 standard frequencies 0.01 ps/mV 200 fs ±20, ±25, ±30, ±50 Up to -40 to +105 2.0x1.6, 2.5x2.0, 3.2x2.5
SiT9366
SiT9367
1 to 220 MHz
220 to 725 MHz
0.05 ps/mV 0.23 ps ±10, ±20, ±25, ±50 Up to -40 to +105 3.2x2.5, 5.0x3.2, 7.0x5.0
SiT9365 32 standard frequencies 0.05 ps/mV 0.23 ps ±10, ±20, ±25, ±50 Up to -40 to +105 3.2x2.5, 5.0x3.2, 7.0x5.0
SiT9120 31 standard frequencies 0.3 ps/mV 0.6 ps ±10, ±20, ±25, ±50 Up to -40 to +85 3.2x2.5, 5.0x3.2, 7.0x5.0
SiT9121
SiT9122
1 to 220 MHz
220 to 625 MHz
0.3 ps/mV 0.6 ps ±10, ±20, ±25, ±50 Up to -40 to +85 3.2x2.5, 5.0x3.2, 7.0x5.0

 

Better resistance to power supply noise

Lowest Jitter Sensitivity to Supply Noise

Lowest Jitter Sensitivity to Broadband Supply Noise

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Lowest Jitter Sensitivity to Supply Noise graph
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Best Jitter Immunity to Broadband Supply Noise graph

SiTime MEMS-based oscillators with multiple internal voltage regulators

As systems adopt smaller form factors and become denser, immunity to power supply noise becomes increasingly important. There are lots of fast edges on the board that create crosstalk and jitter. This noise is amplified when the power supply and other devices on the board turn on or off during operation.

It is important to understand the power supply immunity of clocks, especially in real-word conditions. Quartz oscillator specifications are often based on lab tests that use a very clean power supply. However, actual systems can have noisier power supplies.

Noise can be filtered with passive filters and decoupling capacitors placed near the power supply input of the oscillator. But some noise remains. And this can increase jitter on the output clock, negatively impacting system timing margins and leading to higher error rates.

To solve these problems, SiTime integrates multiple on-chip regulators to filter power supply noise and protect the oscillator. This improves system performance and reduces component count.

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integrated regulators in sitime oscillators
Clock Jitter in High-speed Serial Links
Jitter a concern in your design? Watch our FREE on-demand course

Clock Jitter in High-speed Serial Links

Learn about: jitter propagation through a serial link, selecting a SerDes reference clock, power-supply induced jitter, measuring jitter, and more.

Enroll for class now

Additional Resources

• Application Note: AN10006 Best Design and Layout Practices – Learn about proper decoupling, bypassing, noise rejection, and power supply condition recommendations for SiTime single-ended and differential oscillators.

• Application Note: AN10029 Output Terminations for Differential Oscillators – Learn about termination recommendations for SiTime differential oscillators to ensure optimal performance.

• Technology Paper: Resilience and Reliability of Silicon MEMS Oscillators – Learn about comparative tests conducted on quartz and Silicon MEMS oscillators measuring power supply noise and other environmental stressors.

• Application Note: AN20003 Cascade SiT9514x Power Supply Noise Rejection – Learn about power supply noise rejection (PSNR) performance of the SiT9514x clocks, plus layout guidelines and best practices.

 

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