PAM4 for High-Speed Links

100G, 400G, 800G optical module, oscillator, differential

Datacenters are deploying higher throughout links to accommodate increasing bandwidth demands. This is making the timing margin in transceivers more important, while at the same time, formfactors are shrinking and operating environments are becoming denser and hotter.

SiTime precision timing solutions are ideal for high-speed links, 400Gbps and higher. These MEMS-based devices meet demanding jitter requirement in small footprint packages, and have excellent immunity to temperature transients, power supply noise, and other environmental hazards.

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SiTime MEMS Timing Benefits

Complete MEMS clock tree

Low jitter differential MEMS XO

Low jitter clock generator

More robust in real-world conditions

105°C, resistant to airflow and heat

Immunity to power supply noise

Better frequency stability and reliability

Small size, easy to use

Small footprints

≤1 mm thin that fits back of a card

No quartz reliability issues

PAM4 based High-Speed Links Block Diagrams

400G Optical module

Multi-port Network Switch SoC

MEMS Timing for PAM4 High-Speed Links

Devices Key Features Key Values
Differential Oscillators
SiT9375  25 to 644.5 MHz,
70 fs Integrated Phase Jitter [1]
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SiT9501  25 to 644.5 MHz,
150 fs Integrated Phase Jitter [1]
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  • ±20 ppm to ±50 ppm frequency stability
  • LVPECL, LVDS, HCSL signaling options
  • 1.8 V to 3.3 V
  • 0.01 ps/mV PSNR 
  • -40°C to 105°C
  • 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5 mm packages
  • Meets demanding jitter requirements
  • Small PCB footprint, easier layout
  • Easy design due to flexibility
  • MEMS reliability
Clock Generator
SiT91211 [2]  1 to 750 MHz,
200 fs Integrated Phase Jitter [1]
SiT91213 [2]  1 to 750 MHz,
90 fs Integrated Phase Jitter [1]
  • 4 differential output clocks
  • ±20 ppm frequency stability
  • LVDS, LVPECL, LPHCSL signaling options
  • 0.01 ps/mV PSRR
  • -40°C to 105°C
  • 4 mm x 4 mm package
  • Simplifies clock tree design with multiple low jitter clocks
  • Programmable clocks add flexibility to complex clocking architectures
  • Better frequency stability and noise immunity in harsh environments
  • Small PCB footprint, compact layout

[1] 12 kHz to 20 MHz integration range;  [2] Contact SiTime for availability

Datacenters require extremely reliable 200Gbps, 400Gbps or higher throughput links to sustain data traffic generated by increasing user application loads in dense rack-based servers. PAM4 stands for pulse amplitude modulation, 4-Level. This is the critical piece of technology that enables high-speed, 400Gbps and 800Gbps links.

Increasing demand for Ethernet bandwidth is pushing networking infrastructure vendors and datacenter vendors towards higher speeds over Ethernet. Most networking infrastructure, like routers, switches and Ethernet links in datacenters, have deployed 400Gbps links and are already planning for 800Gbps links.

High speed Ethernet links (10Gbps and higher) initiated the move towards adopting PAM4 but 400Gbps and 800Gbps rates are impossible to achieve without PAM4. Advances in PCB fabrication technology with tighter tolerances on the signal traces, allowed for PAM4 to be deployed for high-speed SERDES links (56G and 112G) whereas better laser technology allowed for PAM4 to be deployed over fiber optic links.

Telecom infrastructure vendors depend on SiTime MEMS-based oscillators and clock products to meet and exceed the demands for increased data bandwidths from streaming content providers.

MEMS Timing Outperforms Quartz

Ultra-Low Phase Noise, 156.25 MHz

Ultra-Low Phase Noise, 644.53125 MHz

SiTime – Ultra-Low Phase Noise, 156.25 MHz
SiTime – Ultra-Low Phase Noise 644.53125 MHz


Excellent Stability

Better PSNR (Power Supply Noise Rejection)

SiTime – Excellent Stability
SiTime – Better PSNR (Power Supply Noise Rejection)


Higher Reliability

Smallest Packages

SiTime timing devices are up to 50x more reliable than legacy quartz
SiTime – Smallest Packages
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