Gary Giust, PhD

Director of System Architecture

Gary Giust, PhD, is a Director of System Architecture at SiTime. Prior to SiTime, Giust founded JitterLabs, and previously worked at Applied Micro, PhaseLink, Supertex, Cypress Semiconductor, and LSI Logic. Giust is an industry expert on timing, has co-authored a book, is an invited speaker, an internationally published author in trade and refereed journals, and a past Technical Chair for the Ethernet Alliance's backplane subcommittee. He holds 21 patents. Giust obtained a Ph.D. at Arizona State University, Tempe, an MS at the University of Colorado Boulder, and a BS at the University of New Hampshire, Durham, all in electrical engineering.

Articles

100G, 400G, 800G optical module, oscillator, differential

Why It’s Time to Rethink Jitter Analysis of SerDes Reference Clocks in Optical Modules

As optical fiber technology continues to push the limits of data transport speed and efficiency, the challenge falls on silicon SerDes vendors to keep up. One major obstacle? Managing tighter jitter budgets as data rates increase. This article explores why legacy phase jitter analysis falls short and a better way to specify Refclk jitter in SerDes datasets.
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7 min read
Split screen of a 5G tower in cold and hot weather showing the temperature extremes resistance

The Top 8 Influencers of Stability in Precision Timing

Frequency-over-temperature stability on its own isn’t enough to predict the performance of a precision oscillator in a real-life system. In practice, different stability specifications in an oscillator datasheet account for the many factors that contribute to stability, and these specifications must be carefully considered when evaluating a system’s overall stability. Here are the top 8 contributors to overall frequency stability output by a precision oscillator along with performance comparison examples.
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9 min read
Circuit board with CPU

A Modern Approach to Refclk Jitter Analysis for SerDes Applications

In the fast-paced world of high-speed data communication, the importance of accurate reference clock (refclk) jitter analysis cannot be overstated. In this article, we'll explore the limitations of the traditional methodology and introduce a new, practical approach that promises to enhance system performance and simplify refclk selection for SerDes applications.
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5 min read
plots highlighting various offset frequency regions that might dominate the integral of phase noise

How to Identify the Source of Phase Jitter through Phase Noise Plots

To better understand and minimize phase jitter, engineers often rely on phase noise plots. These plots provide a visual representation of the different noise sources influencing phase modulation. This “4-minute clinic” gives you a focused approach for analyzing phase noise plots and detecting the main source of jitter.
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5 min read
Circuit board with CPU

Jitter 101. What you need to know.

Each new generation of technology must conquer the effects of jitter. To do so, jitter must be understood, along with an understanding of what causes it and how best to measure it. We define the three most common types of jitter and provide valuable resources and tools for a deeper understanding.
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6 min read
Abstract waves

Die Elite Super-TCXO-Familie erweitert die Temperaturunterstützung auf 105 °C

Die Elite Super-TCXO-Familie ist die einzige Hochfrequenz-TCXO (1 bis 220 MHz) in der Branche mit einer Frequenzstabilität von ±100 ppb bis 105 °C, die erfolgreich in vielen 4G+- und 5G-Systemen eingesetzt wird und sechs Branchenpreise gewonnen hat um die TCXO-Leistung neu zu definieren.
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