RR-50
Rev. A09
Product Reliability Qualification Report- SiT51XX, SiT53XX and SiT59XX Product Familes
Purpose of Stress Testing
This report summarises production qualification of SiT515X, SiT535X and SiT590X product families. The results of this qualification
qualify SiT5146, SiT5147, SiT5155, SiT5156, SiT5157, SiT5346, SiT5347, SiT5348, SiT5349, SiT5351, SiT5352, SiT5356, SiT5357,
SiT5358, SiT5359, SiT5901, SiT5902, SiT5903, SiT5904, SiT5906, SiT5907, SiT5908, SiT5910, SiT5914 and SiT5915 products for
production release. Qualification testing was done on SiT5156, ceramic 5.0 mmX 3.2 mm, 10 LD package, as a representative
Early Life Results (EFR) JEDEC STD- JESD22 A108
Condition:
Dynamic, 125°C, Vcc (max), 168 hours
2062 Quantity Passed: 2062
Quantity Stressed:
Failure Rate:
0
High Temperature Operating Life (HTOL) JEDEC STD- JESD22 A108
Condition:
Dynamic, 125°C, Vcc (3.63V), 1000 hours
Quantity Stressed: 80
Quantity Passed: 80
0.65 FIT
Quantity Failed:
Note-1
0
Semiconductor FIT Calculation:
Confidence Level :
90%
Ea (activation energy in eV): 0.7
Derating:
25° C
ESD
Human Body Model (HBM) JESD22-A114
Condition:
one +ve and -ve pulse, all pin combinations
Quantity Passed: Failure Rate:
ESD level:
2.0kV
0
Quantity Stressed:
ESD Level testing:
Condition:
3
3
one +ve and -ve pulse, all pin combinations
Quantity Passed:
Quantity Stressed:
5
5
Failure Rate:
ESD levels:
ESD level:
2.5kV (3 units), 3.0 kV (2 units)
Charged Device Model (CDM) JEDC STD-JESD-22 C101
Condition:
one +ve and -ve pulse, all pins
Quantity Passed: 3
750V
0
Quantity Stressed:
3
Failure Rate:
Latch Up
JEDEC STD-JESD78
150mA @ 125°C, Vcc (Vmax=3.63V) and voltage overstress (1.5xVmax=5.44V)
Condition:
Quantity Stressed:
6
Quantity Passed:
6
Failure Rate:
0
0
Note:2
NVM Data Retention
Condition:
NVM High Temp Storage (NVM HTS), 150°C, 500 hours
Quantity Passed: 54 Quantity Failed:
Checkerboard pattern, Specific Custom Pattern
NVM Operating Life (NVM HTOL), Dynamic, 125°C, Vcc (3.63V), 1500 hours
Quantity Stressed: 54
Programing:
Condition:
Quantity Stressed: 80
Quantity Passed: 80
Quantity Failed:
0
Programing: Checkerboard pattern
Note-2
Mechanical Shock (MS) MIL-STD-883 Method 2002
Condition: Peak acceleration 30kg
Quantity Stressed: 40 Quantity Passed: 40
Failure Rate:
0
Variable Frequency Vibration (VFV) MIL-STD-883 Method 2007
Condition: Peak acceleration 70g
Quantity Stressed: 40 Quantity Passed: 40
Failure Rate:
Failure Rate:
Failure Rate:
0
0
0
Note-3
Vibration Fatigue (VF) MIL-STD-883 Method 2005
Condition: Peak acceleration 20g, 30 hours
Quantity Stressed: 40 Quantity Passed: 40
Constant Acceleration (CA) MIL-STD-883 Method 2001
Condition: Y1 plane, 30kg
Quantity Stressed: 40 Quantity Passed: 40
RR-50
Rev. A09
Product Information
Wafer Fabrication
TSMC ,
Factory: CMOS:
Taiwan
BOSCH,
Germany Process :PFD2_A
Process: 1P6M CMOS-8"
Design Rule:
Design Rule:
0.18 um
0.25 um
Factory: MEMS:
Notes:
1
. The oscillator family failure rate of 0.65 FIT, calculated based on large cumulative HTOL sample size, applies
due to process technology and design rule similarity.
. Data sharing is done with SiT9365 product due to design and structural similarity of the MEMS die
2