{ "devices": [ { "product_name": "SiT92208", "product_type": "8‑Output Differential Ultra‑Low‑Jitter Buffer (40‑QFN 6×6 mm)", "overview": { "description": "2.1 GHz 8‑output low‑jitter fan‑out buffer with 3:1 input selection and REFOUT; two 4‑output differential banks A,B; pin‑controlled output standards.", "features": [ "Additive jitter ≈55 fs RMS", "Universal inputs (LVPECL/LVDS/LVCMOS/CML‑AC/HCSL/SSTL); DC–2.1 GHz", "Crystal 8–50 MHz; overdrive to 250 MHz (OSC pins ≤1.8 Vpp)", "Max output frequency: LVPECL/LVDS 2.1 GHz, HCSL 700 MHz, LVCMOS 250 MHz", "Typical output skew 30 ps; PSRR up to −70 dBc", "Core 3.3/2.5 V; outputs 3.3/2.5 V (HCSL/REFOUT support 1.8 V)", "Package: 40‑QFN 6×6 mm" ], "applications": [ "Clock distribution", "PCIe trees", "Level translation" ] }, "electrical_characteristics": { "absolute_maximum": { "VCC_V": { "min": -0.3, "max": 3.6 }, "VCCO_V": { "min": -0.3, "max": 3.6 }, "VIN_non_osc_V": { "min": -0.3, "max": 3.6 }, "OSCIN_V_max": 1.8, "storage_temperature_°C": { "min": -55, "max": 150 }, "MSL": 3 }, "recommended_operating": { "VCC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 } ], "VCCO_AB_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "VCCOC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "ambient_temperature_°C": { "min": -40, "max": 85 }, "junction_temperature_°C_max": 125 }, "current_consumption": { "ICC_core_mA": { "typ": 16.5, "max": 19.8 }, "ICC_core_XO_selected_mA_max": 14, "ICC_dyn_at_2100MHz_mA": { "typ": 25, "max": 33 }, "ICCO_bank_mA": { "LVPECL": { "typ": 137, "max": 164 }, "LVDS": { "typ": 40, "max": 49 }, "HCSL": { "typ": 93, "max": 112 } }, "ICCO_LVCMOS_200MHz_mA": { "VCCO_3V3": { "typ": 6, "max": 7.2 }, "VCCO_2V5": { "typ": 4.5, "max": 5.5 } } }, "psrr_dBc_typ": { "LVPECL": -67, "LVDS": -70, "HCSL": -67.7 }, "inputs": { "frequency_range_MHz": { "min": 0, "max": 2100 }, "single_ended_VIH_V_min": { "VCC_3V3": 2.0, "VCC_2V5": 1.6 }, "single_ended_VIL_V_max": { "VCC_3V3": 1.3, "VCC_2V5": 0.9 }, "single_ended_swing_Vpp": { "min": 0.3, "max": 2.0 }, "differential_swing_VID_V": { "min": 0.15, "max": 1.3 } }, "crystal": { "frequency_range_MHz": { "min": 8, "max": 50 }, "overdrive_external_clock_MHz_max": 250, "CL_pF": { "min": 6, "typ": 8, "max": 10 }, "ESR_Ω": { "typ": 35, "max": 60 }, "Co_pF": { "typ": 2, "max": 3 }, "drive_level_µW": { "typ": 100, "max": 200 }, "crystal_phase_jitter_fs_rms_typ": 155 }, "outputs": { "LVPECL": { "fmax_MHz": { "≥600mV": 1200, "≥400mV": 2100 }, "jitter_fs_rms_typ": 55, "duty_cycle_%": [ 45, 55 ], "tpd_ps": { "typ": 700, "max": 900 } }, "LVDS": { "fmax_MHz": { "≥250mV": 1600, "≥200mV": 2100 }, "jitter_fs_rms_typ": 60, "duty_cycle_%": [ 45, 55 ], "tpd_ps": { "typ": 700, "max": 900 }, "skew_ps_typ": 30 }, "HCSL": { "fmax_MHz": 700, "jitter_fs_rms_typ": 55, "duty_cycle_%": [ 45, 55 ], "tpd_ps": { "typ": 700, "max": 900 } }, "LVCMOS": { "fmax_MHz": 250, "jitter_fs_rms_typ": { "VCCO_3V3": 55, "VCCO_2V5": 63 }, "duty_cycle_%": { "≤200MHz": [ 45, 55 ], "\u003e200–250MHz": [ 40, 60 ] }, "tr_tf_ps": { "typ": 250, "max": 450 } } } }, "package": { "options": [ "40‑QFN 6×6 mm" ] }, "ordering_information": { "example": "SiT92208 A I − P", "fields": { "family": "SiT92208", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "CLKOUTA0", "type": "Output", "function": "Bank A0 P — differential output; type set by CLK OUT A_TYPE" }, { "number": 2, "name": "CLKOUTA0*", "type": "Output", "function": "Bank A0 N — differential output; type set by CLK OUT A_TYPE" }, { "number": 4, "name": "CLKOUTA1", "type": "Output", "function": "Bank A1 P — differential output; type set by CLK OUT A_TYPE" }, { "number": 5, "name": "CLKOUTA1*", "type": "Output", "function": "Bank A1 N — differential output; type set by CLK OUT A_TYPE" }, { "number": 7, "name": "CLKOUTA2", "type": "Output", "function": "Bank A2 P — differential output; type set by CLK OUT A_TYPE" }, { "number": 8, "name": "CLKOUTA2*", "type": "Output", "function": "Bank A2 N — differential output; type set by CLK OUT A_TYPE" }, { "number": 9, "name": "CLKOUTA3", "type": "Output", "function": "Bank A3 P — differential output; type set by CLK OUT A_TYPE" }, { "number": 10, "name": "CLKOUTA3*", "type": "Output", "function": "Bank A3 N — differential output; type set by CLK OUT A_TYPE" }, { "number": 30, "name": "CLKOUTB0", "type": "Output", "function": "Bank B0 P — differential output; type set by CLK OUT B_TYPE" }, { "number": 29, "name": "CLKOUTB0*", "type": "Output", "function": "Bank B0 N — differential output; type set by CLK OUT B_TYPE" }, { "number": 27, "name": "CLKOUTB1", "type": "Output", "function": "Bank B1 P — differential output; type set by CLK OUT B_TYPE" }, { "number": 26, "name": "CLKOUTB1*", "type": "Output", "function": "Bank B1 N — differential output; type set by CLK OUT B_TYPE" }, { "number": 24, "name": "CLKOUTB2", "type": "Output", "function": "Bank B2 P — differential output; type set by CLK OUT B_TYPE" }, { "number": 23, "name": "CLKOUTB2*", "type": "Output", "function": "Bank B2 N — differential output; type set by CLK OUT B_TYPE" }, { "number": 22, "name": "CLKOUTB3", "type": "Output", "function": "Bank B3 P — differential output; type set by CLK OUT B_TYPE" }, { "number": 21, "name": "CLKOUTB3*", "type": "Output", "function": "Bank B3 N — differential output; type set by CLK OUT B_TYPE" }, { "number": 36, "name": "REFOUT", "type": "Output", "function": "LVCMOS clock out synchronized to selected clock; enable via REFOUT_EN" }, { "number": 16, "name": "CLKIN0", "type": "Input", "function": "Universal clock input 0 (+) — differential/single‑ended" }, { "number": 17, "name": "CLKIN0*", "type": "Input", "function": "Universal clock input 0 (−) — differential/single‑ended" }, { "number": 34, "name": "CLKIN1", "type": "Input", "function": "Universal clock input 1 (+) — differential/single‑ended" }, { "number": 33, "name": "CLKIN1*", "type": "Input", "function": "Universal clock input 1 (−) — differential/single‑ended" }, { "number": 13, "name": "OSCIN", "type": "Input", "function": "Crystal input; can accept AC‑coupled single‑ended overdrive (≤1.8 Vpp)" }, { "number": 14, "name": "OSCOUT", "type": "Output", "function": "Crystal output; leave floating if OSCIN is driven by single‑ended clock" }, { "number": 12, "name": "VCC", "type": "Power", "function": "Core supply 3.3/2.5 V" }, { "number": 35, "name": "VCC", "type": "Power", "function": "Core supply 3.3/2.5 V" }, { "number": 3, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V" }, { "number": 6, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V" }, { "number": 25, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V" }, { "number": 28, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V" }, { "number": 37, "name": "VCCOC", "type": "Power", "function": "REFOUT supply 3.3/2.5/1.8 V" }, { "number": 0, "name": "GND-EPAD", "type": "Ground", "function": "Exposed pad ground" }, { "number": 20, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 31, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 40, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 11, "name": "CLK OUT A_Type0", "type": "Control", "function": "Bank A output type select (with Type1)" }, { "number": 39, "name": "CLKOUTA_Type1", "type": "Control", "function": "Bank A output type select (with Type0)" }, { "number": 19, "name": "CLK OUT B_Type0", "type": "Control", "function": "Bank B output type select (with Type1)" }, { "number": 32, "name": "CLK OUT B_Type1", "type": "Control", "function": "Bank B output type select (with Type0)" }, { "number": 38, "name": "REFOUT_EN", "type": "Control", "function": "Enable LVCMOS REFOUT (glitch‑free enable/disable)" }, { "number": 15, "name": "CLK IN_SEL0", "type": "Control", "function": "Clock input select bit 0" }, { "number": 18, "name": "CLKIN_SEL1", "type": "Control", "function": "Clock input select bit 1" } ] }, { "product_name": "SiT92216", "product_type": "4 Differential + 1 LVCMOS Ultra‑Low‑Jitter Buffer (32‑QFN 5×5 mm)", "overview": { "description": "High‑performance buffer with 4 differential outputs and 1 LVCMOS, 3:1 input mux (2 universal + crystal), PCIe Gen1–Gen6 capable; no supply sequencing required.", "features": [ "Additive jitter ≈50 fs RMS", "Universal inputs (LVPECL/LVDS/LVCMOS/SSTL/HCSL/OSC); DC–2.1 GHz", "Crystal bypass overdrive up to 250 MHz; OSC pins ≤1.5 V", "REFOUT LVCMOS; outputs selectable LVPECL/LVDS/HCSL/Hi‑Z", "Typical output skew 30 ps; noise floor −159 dBc/Hz", "Core 3.3/2.5 V; outputs 3.3/2.5 V; 1.8 V supported for HCSL and LVCMOS", "Package: 32‑QFN 5×5 mm" ], "applications": [ "Carrier Ethernet", "5G base stations/small cells", "Data center clocking" ] }, "electrical_characteristics": { "absolute_maximum": { "VCC_V": { "min": -0.3, "max": 3.6 }, "VCCO_V": { "min": -0.3, "max": 3.6 }, "VIN_non_osc_V": { "min": -0.3, "max": 3.6 }, "OSCIN_V_max": 1.5, "storage_temperature_°C": { "min": -55, "max": 150 }, "MSL": 3 }, "recommended_operating": { "VCC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 } ], "VCCO_AB_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "VCCOC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "ambient_temperature_°C": { "min": -40, "max": 85 }, "junction_temperature_°C_max": 125 }, "current_consumption": { "ICC_core_mA": { "typ": 16.5, "max": 19.8 }, "ICC_core_XO_selected_mA": { "typ": 11.4, "max": 14 }, "ICC_dyn_at_2100MHz_mA": { "typ": 25, "max": 33 }, "ICCO_bank_mA": { "LVPECL": { "typ": 82, "max": 97.2 }, "LVDS": { "typ": 40, "max": 49 }, "HCSL": { "typ": 59, "max": 70.8 } }, "ICCO_LVCMOS_200MHz_mA": { "VCCO_3V3": { "typ": 6, "max": 7.2 }, "VCCO_2V5": { "typ": 4.5, "max": 5.5 } } }, "psrr_dBc_typ": { "LVPECL": -67, "LVDS": -70, "HCSL": -67.7 }, "inputs": { "frequency_range_MHz": { "min": 0, "max": 2100 }, "single_ended_VIH_V_min": { "VCC_3V3": 2.0, "VCC_2V5": 1.6 }, "single_ended_VIL_V_max": { "VCC_3V3": 1.3, "VCC_2V5": 0.9 }, "single_ended_swing_Vpp": { "min": 0.3, "max": 2.0 }, "differential_swing_VID_V": { "min": 0.15, "max": 1.3 } }, "crystal": { "frequency_range_MHz": { "min": 8, "max": 50 }, "overdrive_external_clock_MHz_max": 250, "CL_pF": { "min": 6, "typ": 8, "max": 10 }, "ESR_Ω": { "typ": 35, "max": 60 }, "Co_pF": { "typ": 2, "max": 3 }, "drive_level_µW": { "typ": 100, "max": 200 }, "crystal_phase_jitter_fs_rms_typ": 155 }, "outputs": { "LVPECL": { "fmax_MHz": { "≥600mV": 1200, "≥400mV": 2100 }, "jitter_fs_rms_typ": [ 55, 88 ], "duty_cycle_%": [ 45, 55 ], "tr_tf_ps_typ": 210 }, "LVDS": { "fmax_MHz": { "≥250mV": 1600, "≥200mV": 2100 }, "jitter_fs_rms_typ": [ 60, 82 ], "duty_cycle_%": [ 45, 55 ] }, "HCSL": { "fmax_MHz": 700, "jitter_fs_rms_typ": [ 55, 86 ], "duty_cycle_%": [ 45, 55 ] }, "LVCMOS": { "fmax_MHz": 250, "jitter_fs_rms_typ": { "VCCO_3V3": [ 22, 45 ], "VCCO_2V5": [ 24, 43 ] }, "duty_cycle_%": { "≤200MHz": [ 45, 55 ], "\u003e200–250MHz": [ 40, 60 ] }, "tr_tf_ps": { "typ": 250, "max": 450 } } }, "prop_delay_and_skew": { "tpd_ps": { "LVPECL": { "min": 723, "typ": 818, "max": 931 }, "LVDS": { "min": 726, "typ": 826, "max": 944 }, "HCSL": { "min": 705, "typ": 820, "max": 897 } }, "LVCMOS_td_ns": { "VCCO_3V3": { "typ": 1.4, "max": 2.5 }, "VCCO_2V5": { "typ": 1.5, "max": 2.7 } }, "skew_ps_max": 31 } }, "package": { "options": [ "32‑QFN 5×5 mm" ] }, "ordering_information": { "example": "SiT92216 A I − P", "fields": { "family": "SiT92216", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": "DAP", "name": "DAP", "type": "Ground", "function": "Die attach pad; connect to PCB ground plane" }, { "number": 1, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 8, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 17, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 24, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 2, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 5, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 3, "name": "CLKOUTA0", "type": "Output", "function": "Bank A0 differential output (P)" }, { "number": 4, "name": "CLKOUTA0*", "type": "Output", "function": "Bank A0 differential output (N)" }, { "number": 6, "name": "CLKOUTA1", "type": "Output", "function": "Bank A1 differential output (P)" }, { "number": 7, "name": "CLKOUTA1*", "type": "Output", "function": "Bank A1 differential output (N)" }, { "number": 9, "name": "CLKOUT_TYPE0", "type": "Control", "function": "Output driver type select (with TYPE1)" }, { "number": 32, "name": "CLKOUT_TYPE1", "type": "Control", "function": "Output driver type select (with TYPE0)" }, { "number": 10, "name": "VCC", "type": "Power", "function": "Core/Input supply 3.3/2.5 V" }, { "number": 28, "name": "VCC", "type": "Power", "function": "Core/Input supply 3.3/2.5 V" }, { "number": 11, "name": "OSCIN", "type": "Input", "function": "Crystal input or external XO/TCXO single‑ended" }, { "number": 12, "name": "OSCOUT", "type": "Output", "function": "Crystal output; leave floating if OSCIN is driven" }, { "number": 13, "name": "CLKIN_SEL0", "type": "Control", "function": "Clock input select bit 0" }, { "number": 16, "name": "CLKIN_SEL1", "type": "Control", "function": "Clock input select bit 1" }, { "number": 14, "name": "CLKIN0", "type": "Input", "function": "Universal clock input 0 (differential/single‑ended)" }, { "number": 15, "name": "CLKIN0*", "type": "Input", "function": "Universal clock input 0 complement" }, { "number": 18, "name": "CLKOUTB1*", "type": "Output", "function": "Bank B1 differential output (N)" }, { "number": 19, "name": "CLKOUTB1", "type": "Output", "function": "Bank B1 differential output (P)" }, { "number": 20, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 23, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 21, "name": "CLKOUTB0*", "type": "Output", "function": "Bank B0 differential output (N)" }, { "number": 22, "name": "CLKOUTB0", "type": "Output", "function": "Bank B0 differential output (P)" }, { "number": 25, "name": "NC", "type": "NC", "function": "No connect" }, { "number": 26, "name": "CLKIN1*", "type": "Input", "function": "Universal clock input 1 complement" }, { "number": 27, "name": "CLKIN1", "type": "Input", "function": "Universal clock input 1" }, { "number": 29, "name": "REFOUT", "type": "Output", "function": "LVCMOS reference clock output" }, { "number": 30, "name": "VCCOC", "type": "Power", "function": "REFOUT supply 3.3/2.5/1.8 V" }, { "number": 31, "name": "REFOUT_EN", "type": "Control", "function": "Enable REFOUT (synchronized, glitch‑free)" } ] }, { "product_name": "SiT95141", "product_type": "Cascade ClkSoC – Low‑jitter 10‑output MEMS Clock Generator (64‑QFN 9×9 mm)", "overview": { "description": "Single‑chip MEMS clock generator with integrated ApexMEMS® resonator, quad fractional‑N PLLs and up to 10 differential (or 20 LVCMOS) low‑jitter outputs. Eliminates external crystal, simplifies design, supports flexible input→output translation (8 kHz to 2.1 GHz).", "features": [ "Quad fractional‑N PLLs with integrated VCO and loop filter; typ 93 fs RMS (4‑16A) for SerDes; 127 fs RMS (12 k–20 M) example", "10 differential or 20 LVCMOS outputs; individually programmable format: LVPECL, LVPECL2, LVDS, LVDS‑Boost, HCSL, CML, or LVCMOS", "Output frequency support: differential 8 kHz–2.1 GHz; LVCMOS 8 kHz–250 MHz; 1 Hz–2.1 GHz on OUT0", "Input support: differential 8 kHz–2.1 GHz; LVCMOS 8 kHz–250 MHz; min slew 400 V/µs", "Programmable output delay control (35 ps step; ~7.5 ns range); cross‑PLL phase sync ±250 ps", "DCO mode via I²C/SPI with 0.005 ppb resolution; ±100 ppm max step", "Optional external zero‑delay mode on one PLL (typ ~100 ps I/O delay; ~1 ps/°C temp drift)", "Fixed PLL bandwidth 4 kHz; jitter peaking ≤0.1 dB (SONET)", "Indicators: Clock Loss (2/4/8/16 pulses), Lock Loss (±0.2…±4000 ppm) on FLEXIO/INTRB", "Two OTP banks (primary \u0026 secondary) + in‑system I²C/SPI configuration; factory pre‑program option" ], "applications": [ "Clock tree consolidation (replace XOs/buffers)", "Low‑jitter frequency translation \u0026 generation", "10G/100G/400G Ethernet \u0026 OTN clocking", "FPGA/processor/memory clocking; servers/storage/datacenter", "Test \u0026 measurement; broadcast video" ] }, "electrical_characteristics": { "inputs": { "count_diff": 4, "count_single_ended": 4, "frequency_range": { "differential_MHz_min": 0.008, "differential_MHz_max": 2100, "single_ended_MHz_min": 0.008, "single_ended_MHz_max": 250 }, "swing_requirements_mVpp": { "lt_400MHz": 100, "400to750MHz": 225, "gt_750MHz": 350 }, "single_ended_ac_mVpp": { "min": 500, "max": 3600 }, "slew_rate_min_V_per_us": 400, "duty_cycle_percent": [ 40, 60 ] }, "outputs": { "count_diff": 10, "count_lvcmos_pairs": 20, "frequency_range": { "diff_Hz_min": 1, "diff_Hz_max": 2100000000, "hcsL_Hz_max": 700000000, "lvcmos_Hz_min": 1, "lvcmos_Hz_max": 250000000, "out0_special_min_Hz": 1, "out0_special_max_Hz": 2100000000 }, "pll_loop_bandwidth_Hz": 4000, "duty_cycle_percent": [ 45, 55 ], "rise_fall_time_limits": { "lvcmos_ns_max": { "1p8V": 2.0, "2p5V": 1.5, "3p3V": 1.2 }, "diff_ps_max": 350 }, "phase": { "output_delay_step_ps": 35, "output_delay_range_ns": 7.5, "cross_pll_sync_ps_max": 250 }, "standards": [ "LVPECL", "LVPECL2", "LVDS", "LVDS-Boost", "HCSL", "CML", "LVCMOS" ] }, "jitter": { "rms_fs_typ_4_16A": 93, "rms_fs_typ_12k_20M": 127, "rms_fs_typ_4_20_at_312p5MHz": 62, "close_in_phase_noise_dBc_per_Hz_typ_at_122p88MHz": { "10Hz": -91, "100Hz": -113, "1kHz": -130, "10kHz": -138 } }, "psrr_dBc_typ": { "VDD_3p3V": -96, "VDD_2p5V": -90, "VDD_1p8V": -75, "VDDIN": -70, "VDDO": -80 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "dco": { "resolution_ppb": 0.005, "max_step_ppm": 100 }, "holdover": { "frequency_stability_ppm_max": 45, "aging_10yr_ppm_typ": 2 }, "io_logic": { "i2c_slave_default_address": "0x69", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20 } }, "pins": [ { "number": 63, "name": "IN0P", "type": "Input", "function": "True input for IN0 diff / LVCMOS" }, { "number": 64, "name": "IN0N", "type": "Input", "function": "Complement for IN0 diff; AC‑coupled; cap‑to‑GND for LVCMOS" }, { "number": 1, "name": "IN1P", "type": "Input", "function": "True input for IN1 diff / LVCMOS" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Complement for IN1 diff; cap‑to‑GND for LVCMOS" }, { "number": 14, "name": "IN2P", "type": "Input", "function": "True input for IN2 diff / LVCMOS" }, { "number": 15, "name": "IN2N", "type": "Input", "function": "Complement for IN2 diff; cap‑to‑GND for LVCMOS" }, { "number": 61, "name": "IN3P", "type": "Input", "function": "True input for IN3 diff / LVCMOS / ZDB feedback" }, { "number": 62, "name": "IN3N", "type": "Input", "function": "Complement for IN3 diff; cap‑to‑GND for LVCMOS / ZDB feedback" }, { "number": 28, "name": "OUT0P", "type": "Output", "function": "Output 0 + / LVCMOS" }, { "number": 27, "name": "OUT0N", "type": "Output", "function": "Output 0 − / LVCMOS" }, { "number": 24, "name": "OUT0BP", "type": "Output", "function": "Output 0B + / LVCMOS" }, { "number": 23, "name": "OUT0BN", "type": "Output", "function": "Output 0B − / LVCMOS" }, { "number": 59, "name": "OUT0TP", "type": "Output", "function": "Output 0T + / LVCMOS" }, { "number": 58, "name": "OUT0TN", "type": "Output", "function": "Output 0T − / LVCMOS" }, { "number": 31, "name": "OUT1P", "type": "Output", "function": "Output 1 + / LVCMOS" }, { "number": 30, "name": "OUT1N", "type": "Output", "function": "Output 1 − / LVCMOS" }, { "number": 35, "name": "OUT2P", "type": "Output", "function": "Output 2 + / LVCMOS" }, { "number": 34, "name": "OUT2N", "type": "Output", "function": "Output 2 − / LVCMOS" }, { "number": 38, "name": "OUT3P", "type": "Output", "function": "Output 3 + / LVCMOS" }, { "number": 37, "name": "OUT3N", "type": "Output", "function": "Output 3 − / LVCMOS" }, { "number": 42, "name": "OUT4P", "type": "Output", "function": "Output 4 + / LVCMOS" }, { "number": 41, "name": "OUT4N", "type": "Output", "function": "Output 4 − / LVCMOS" }, { "number": 45, "name": "OUT5P", "type": "Output", "function": "Output 5 + / LVCMOS" }, { "number": 44, "name": "OUT5N", "type": "Output", "function": "Output 5 − / LVCMOS" }, { "number": 51, "name": "OUT6P", "type": "Output", "function": "Output 6 + / LVCMOS" }, { "number": 50, "name": "OUT6N", "type": "Output", "function": "Output 6 − / LVCMOS" }, { "number": 54, "name": "OUT7P", "type": "Output", "function": "Output 7 + / LVCMOS" }, { "number": 53, "name": "OUT7N", "type": "Output", "function": "Output 7 − / LVCMOS" }, { "number": 13, "name": "VDDIN", "type": "Power", "function": "Analog/input supply" }, { "number": 46, "name": "VDD", "type": "Power", "function": "PLL digital supply" }, { "number": 60, "name": "VDD", "type": "Power", "function": "PLL digital supply" }, { "number": 22, "name": "VDDO0B", "type": "Power", "function": "Output bank 0B supply" }, { "number": 26, "name": "VDDO0", "type": "Power", "function": "Output bank 0 supply" }, { "number": 29, "name": "VDDO1", "type": "Power", "function": "Output bank 1 supply" }, { "number": 33, "name": "VDDO2", "type": "Power", "function": "Output bank 2 supply" }, { "number": 36, "name": "VDDO3", "type": "Power", "function": "Output bank 3 supply" }, { "number": 40, "name": "VDDO4", "type": "Power", "function": "Output bank 4 supply" }, { "number": 43, "name": "VDDO5", "type": "Power", "function": "Output bank 5 supply" }, { "number": 49, "name": "VDDO6", "type": "Power", "function": "Output bank 6 supply" }, { "number": 52, "name": "VDDO7", "type": "Power", "function": "Output bank 7 supply" }, { "number": 57, "name": "VDDO0T", "type": "Power", "function": "Output bank 0T supply" }, { "number": 12, "name": "INTRB", "type": "Output", "function": "Active‑LOW aggregated sticky notify" }, { "number": 11, "name": "OEB", "type": "Input", "function": "Output disable (HIGH)" }, { "number": 6, "name": "RSTB", "type": "Input", "function": "Reset (active‑LOW); on‑chip 25 kΩ pull‑up to VDDIO" }, { "number": 3, "name": "IN_SEL0", "type": "Input", "function": "Manual input clock select bit 0" }, { "number": 4, "name": "IN_SEL1", "type": "Input", "function": "Manual input clock select bit 1" }, { "number": 18, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI SDI" }, { "number": 16, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI SCLK" }, { "number": 19, "name": "CSB/A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "SDO/A1", "type": "I/O", "function": "SPI SDO / I²C A1" }, { "number": 39, "name": "I2C1_SPI0", "type": "Input", "function": "Serial interface select: 1=I²C, 0=SPI" }, { "number": -1, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "storage_temperature_C": { "min": -55, "max": 150 }, "junction_temperature_C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V": 2000, "ESD_CDM_V": 750, "latchup_mA": 100, "MSL": 3 }, "package": { "options": [ "64‑QFN, 9×9 mm" ], "notes": [ "Integrated MEMS resonator (no external crystal required)", "Use recommended AC/DC terminations per output standard; LVDS/LVDS‑Boost preferred for AC‑coupled", "RSTB, FLEXIO inputs, I²C/SPI inputs at 1.8 V require series resistor (≈4.7 kΩ) if driving from 2.5/3.3 V" ] }, "ordering_information": { "example": "SiT95141 A I - X Y Y Y Y Y - T", "fields": { "family": "SiT95141", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X/Y characters = pre‑programmed startup config ID", "packaging": { "T": "Tape \u0026 Reel (various ku options)" } } } }, { "product_name": "SiT95145", "product_type": "Cascade ClkSoC – High‑Performance 10‑output MEMS Jitter Cleaner", "overview": { "description": "Single‑chip MEMS clock jitter cleaner with quad fractional‑N PLLs and up to 10 differential (or 20 LVCMOS) low‑jitter outputs. Integrates SiTime ApexMEMS resonator—no external crystal—supporting flexible input‑to‑output frequency translation from 8 kHz to 2.1 GHz.", "key_features": [ "4 fractional‑N PLLs with integrated VCO/loop filter; ~93 fs typ RMS phase jitter (4‑16A method) for SerDes", "10 differential / 20 LVCMOS outputs; per‑output format and VDDO (1.8/2.5/3.3 V)", "Input support: differential 8 kHz–750 MHz; single‑ended/LVCMOS 8 kHz–250 MHz", "Output support: differential 8 kHz–2.1 GHz; LVCMOS 8 kHz–250 MHz; one output supports down to 1 Hz", "Programmable jitter‑attenuation bandwidth per PLL: 1 mHz–4 kHz", "Hitless input switching, phase build‑out/propagation, frequency ramping for plesiochronous clocks", "Holdover \u0026 synchronized/free‑run modes; DCO mode with 0.005 ppb frequency step resolution", "Programmable output delay: 35 ps step, up to 7.5 ns; zero‑delay buffer mode", "Fault monitors: Clock Loss, Frequency Drift (fine/coarse), Lock Loss; sticky notify \u0026 status via FLEXIO", "9×9 mm 64‑pin PQFN; two‑time programmable NVM; I2C/SPI control; factory pre‑programmable startup" ], "applications": [ "Clock tree consolidation; XO/buffer replacement", "10G/100G/400G Ethernet; SyncE (G.8262.1)", "IEEE 1588 PTP systems", "JESD204B/C device and SYSREF clocking", "OTN, data center, servers, storage", "FPGA/ASIC/SoC and memory clocking", "Test \u0026 measurement; broadcast video" ] }, "electrical_characteristics": { "inputs": { "differential_freq_range_Hz": [ 8000, 2100000000 ], "single_ended_freq_range_Hz": [ 8000, 250000000 ], "diff_min_swing_mVpk": { "\u003c400MHz": 100, "400–750MHz": 225, "\u003e750MHz": 350 }, "single_ended_ac_coupled_range_mVpp": [ 500, 3600 ], "duty_cycle_percent": [ 40, 60 ], "slew_rate_min_V_per_us": 400, "input_capacitance_pF_typ": 0.3, "input_resistance_kohm_typ": { "ac_coupled_se": 15, "differential": 10 }, "lvcmos_dc_thresholds_V": { "VIH_min": 0.8, "VIL_max": 0.4 } }, "outputs": { "frequency_ranges": { "differential_Hz": [ 8000, 2100000000 ], "differential_Hz_HCSL": [ 1, 700000000 ], "lvcmos_Hz": [ 1, 250000000 ] }, "stability_ppm_locked_to_internal_MEMS_max": 45, "aging_10year_ppm": 2, "pll_loop_bandwidth_Hz": [ 0.001, 4000 ], "max_phase_hit_ps": 50, "output_delay_resolution_ps": 35, "output_delay_range_ns": 7.5 }, "jitter": { "free_run": { "rms_phase_jitter_fs_typ_4_16A": 93, "rms_phase_jitter_fs_typ_12k_20M": 127 }, "translation_mode": { "rms_phase_jitter_fs_typ_12k_20M": 120, "note": "Typical @ FOUT 622.08 MHz, FIN 10 MHz, single‑PLL; excludes input clock noise" } }, "supplies": { "vddin_V_ranges": [ [ 2.375, 2.625 ], [ 2.97, 3.63 ] ], "vdd_pll_V_ranges": [ [ 1.71, 1.89 ], [ 2.375, 2.625 ], [ 2.97, 3.63 ] ], "vddo_output_banks_V_ranges": [ [ 1.71, 1.89 ], [ 2.375, 2.625 ], [ 2.97, 3.63 ] ], "supply_ramp_ms": { "min": 0.1, "max": 50 }, "total_power_example_mW": 1130, "iddin_mA_typ_max": [ 20, 25 ], "idd_pll_mA_typ_max": { "4_plls_8_out": [ 320, 384 ], "4_plls_10_out": [ 345, 414 ], "2_plls_4_out": [ 170, 204 ] }, "iddo_output_driver_mA_typ_max_examples": { "LVPECL": [ 40, 48 ], "LVPECL2": [ 28, 33.6 ], "CML": [ 20, 24 ], "HCSL": [ 27, 32.4 ], "LVDS": [ 16, 19.2 ], "LVDS_boost": [ 20, 24 ], "LVCMOS_250MHz_2p5V_5pF": [ 15, 18 ] } }, "psnr_dBc_typ": { "VDD_3p3V": -96, "VDD_2p5V": -90, "VDD_1p8V": -75, "VDDIN": -70, "VDDO": -80 } }, "modes": { "operation": [ "free_run", "synchronized", "holdover" ], "hitless_switching": { "phase_build_out": { "max_phase_hit_ps": 50 }, "phase_propagation": { "programmable_slope_us_per_s": [ 10, 40, 160 ] }, "frequency_ramp_ppm_per_s": [ 0.2, 2, 20, 40000 ] }, "dco_mode": { "resolution_ppb": 0.005, "range_ppm": 100 } }, "interfaces": { "i2c": { "speed_kHz_max": 400, "default_address": "0x69", "alternate": [ "0x68", "0x6A", "0x6B" ], "full_addressing_via_reg_0x2A": true }, "spi": { "speed_MHz_max": 20, "frame_bits": 24, "notes": "8‑bit wr/rdn + 8‑bit addr + 8‑bit data" } }, "fault_monitors": { "clock_loss": { "edges_missing_options": [ 2, 4, 8, 16 ] }, "frequency_drift_fine_ppm": { "step": 2, "range": [ 2, 500 ] }, "frequency_drift_coarse_ppm": { "step": 100, "range": [ 100, 1600 ] }, "lock_loss_ppm_thresholds": { "set": [ 0.2, 0.4, 2, 4, 20, 40, 200, 400, 2000, 4000 ], "clear": [ 0.2, 0.4, 2, 200 ] } }, "package": { "package_type": "64‑pin 9×9 mm PQFN (exposed pad)", "thermal": { "theta_JA_C_per_W": { "still_air": 25.5, "airflow_1ms": 20.8, "airflow_2ms": 19.6 }, "theta_JC": 8.7, "theta_JB": 7.07 }, "msl": "MSL3 @ 260°C" }, "absolute_maximum": { "voltage_limits_V": { "VDDIN_max": 3.63, "VDD_max": 3.63, "VDDO_max": 3.63, "VIN_all_inputs_max": 3.63 }, "storage_temp_C": [ -55, 150 ], "max_junction_temp_C": 125, "programming_temp_C": [ 25, 85 ], "esd_HBM_V": 2000, "latchup_mA": 100 }, "ordering_information": { "format": "SiT95145AI- XYYYYY- T", "temp": { "I": "-40 to +85°C" }, "notes": [ "Factory pre‑programmed startup configuration available", "Two‑time programmable NVM for user programming", "Customer serial ID (XYYYYY) options" ] }, "pins_summary": { "inputs": [ "IN0P/N", "IN1P/N", "IN2P/N", "IN3P/N" ], "outputs": [ "OUT0/0B/0T pairs", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7" ], "power": [ "VDDIN", "VDD (core/PLL)", "VDDO[banks]", "GND(e‑pad)" ], "control_status": [ "I2C1_SPI0", "SDAIO", "SCLK", "SDO/A1", "CSB/A0", "RSTB", "OEb", "FLEXIO[3,8,13,14,15]", "INTRB", "LOLB" ], "i2c_default_address": "0x69" } }, { "product_name": "SiT95147", "product_type": "Cascade ClkSoC – High‑Performance 8‑output MEMS Jitter Cleaner, Clock Synchronizer (64‑QFN 9×9 mm)", "overview": { "description": "Single‑chip MEMS jitter cleaner/clock synchronizer with integrated ApexMEMS® resonator, quad fractional‑N PLLs and up to 8 differential (or 16 LVCMOS) low‑jitter outputs. Eliminates external crystal, simplifies design, supports flexible input→output translation (8 kHz to 2.1 GHz).", "features": [ "Quad fractional‑N PLLs with integrated VCO and loop filter; typ 93 fs RMS (4‑16A) for SerDes; 127 fs RMS (12 k–20 M) example", "8 differential or 16 LVCMOS outputs; individually programmable format: LVPECL, LVPECL2, LVDS, LVDS‑Boost, HCSL, CML, or LVCMOS", "Output frequency support: differential 8 kHz–2.1 GHz; LVCMOS 1 Hz–250 MHz; 1 Hz–2.1 GHz available on OUT0", "Input support: differential 8 kHz–2.1 GHz; LVCMOS 8 kHz–250 MHz; min slew 400 V/µs", "Programmable PLL bandwidth 1 mHz–4 kHz; jitter peaking ≤0.1 dB (SONET)", "Programmable output delay control (35 ps step; ~7.5 ns range); cross‑PLL phase sync ±250 ps", "DCO mode via I²C/SPI with 0.005 ppb resolution; ±100 ppm max step", "Zero‑Delay Mode on any PLL (typ ~100 ps input→output delay; ~1 ps/°C temperature variation)", "Indicators: Clock Loss (2/4/8/16 pulses), Lock Loss (±0.2…±4000 ppm), Fine/Coarse Frequency Drift on FLEXIO/INTRB", "Two OTP banks on slaves + in‑system I²C/SPI configuration; factory pre‑program option" ], "applications": [ "Clock tree consolidation (replace XOs/buffers)", "Low‑jitter frequency translation \u0026 generation", "10G/100G/400G Ethernet, IEEE‑1588/PTP, SyncE", "FPGA/processor/memory clocking; servers/storage/datacenter", "OTN, test \u0026 measurement, broadcast video" ] }, "electrical_characteristics": { "inputs": { "count_diff": 4, "count_single_ended": 4, "frequency_range": { "differential_MHz_min": 0.008, "differential_MHz_max": 2100, "single_ended_MHz_min": 0.008, "single_ended_MHz_max": 250 }, "swing_requirements_mVpp": { "lt_400MHz": 100, "400to750MHz": 225, "gt_750MHz": 350 }, "single_ended_ac_mVpp": { "min": 500, "max": 3600 }, "slew_rate_min_V_per_us": 400, "duty_cycle_percent": [ 40, 60 ] }, "outputs": { "count_diff": 8, "count_lvcmos_pairs": 16, "frequency_range": { "diff_Hz_min": 8000, "diff_Hz_max": 2100000000, "hcsL_Hz_max": 700000000, "lvcmos_Hz_min": 1, "lvcmos_Hz_max": 250000000, "out0_special_min_Hz": 1, "out0_special_max_Hz": 2100000000 }, "pll_loop_bandwidth_Hz": 4000, "duty_cycle_percent": [ 45, 55 ], "rise_fall_time_limits": { "lvcmos_ns_max": { "1p8V": 2.0, "2p5V": 1.5, "3p3V": 1.2 }, "diff_ps_max": 350 }, "phase": { "output_delay_step_ps": 35, "output_delay_range_ns": 7.5, "cross_pll_sync_ps_max": 250 }, "standards": [ "LVPECL", "LVPECL2", "LVDS", "LVDS-Boost", "HCSL", "CML", "LVCMOS" ] }, "jitter": { "rms_fs_typ_4_16A": 93, "rms_fs_typ_12k_20M": 127, "rms_fs_typ_4_20_at_312p5MHz": 62, "close_in_phase_noise_dBc_per_Hz_typ_at_122p88MHz": { "10Hz": -91, "100Hz": -113, "1kHz": -130, "10kHz": -138 } }, "psrr_dBc_typ": { "VDD_3p3V": -96, "VDD_2p5V": -90, "VDD_1p8V": -75, "VDDIN": -70, "VDDO": -80 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "dco": { "resolution_ppb": 0.005, "max_step_ppm": 100 }, "holdover": { "frequency_stability_ppm_max": 45, "aging_10yr_ppm_typ": 2 }, "io_logic": { "i2c_slave_default_address": "0x6D", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20 } }, "pins": [ { "number": 63, "name": "IN0P", "type": "Input", "function": "True input for IN0 diff / LVCMOS" }, { "number": 64, "name": "IN0N", "type": "Input", "function": "Complement for IN0 diff; cap‑to‑GND for LVCMOS" }, { "number": 1, "name": "IN1P", "type": "Input", "function": "True input for IN1 diff / LVCMOS" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Complement for IN1 diff; cap‑to‑GND for LVCMOS" }, { "number": 14, "name": "IN2P", "type": "Input", "function": "True input for IN2 diff / LVCMOS" }, { "number": 15, "name": "IN2N", "type": "Input", "function": "Complement for IN2 diff; cap‑to‑GND for LVCMOS" }, { "number": 61, "name": "IN3P", "type": "Input", "function": "True input for IN3 diff / LVCMOS / ZDB feedback" }, { "number": 62, "name": "IN3N", "type": "Input", "function": "Complement for IN3 diff; cap‑to‑GND for LVCMOS / ZDB feedback" }, { "number": 24, "name": "OUT0BP", "type": "Output", "function": "Output 0B + / LVCMOS" }, { "number": 23, "name": "OUT0BN", "type": "Output", "function": "Output 0B − / LVCMOS" }, { "number": 31, "name": "OUT1P", "type": "Output", "function": "Output 1 + / LVCMOS" }, { "number": 30, "name": "OUT1N", "type": "Output", "function": "Output 1 − / LVCMOS" }, { "number": 35, "name": "OUT2P", "type": "Output", "function": "Output 2 + / LVCMOS" }, { "number": 34, "name": "OUT2N", "type": "Output", "function": "Output 2 − / LVCMOS" }, { "number": 38, "name": "OUT3P", "type": "Output", "function": "Output 3 + / LVCMOS" }, { "number": 37, "name": "OUT3N", "type": "Output", "function": "Output 3 − / LVCMOS" }, { "number": 45, "name": "OUT5P", "type": "Output", "function": "Output 5 + / LVCMOS" }, { "number": 44, "name": "OUT5N", "type": "Output", "function": "Output 5 − / LVCMOS" }, { "number": 51, "name": "OUT6P", "type": "Output", "function": "Output 6 + / LVCMOS" }, { "number": 50, "name": "OUT6N", "type": "Output", "function": "Output 6 − / LVCMOS" }, { "number": 54, "name": "OUT7P", "type": "Output", "function": "Output 7 + / LVCMOS" }, { "number": 53, "name": "OUT7N", "type": "Output", "function": "Output 7 − / LVCMOS" }, { "number": 59, "name": "OUT0TP", "type": "Output", "function": "Output 0T + / LVCMOS" }, { "number": 58, "name": "OUT0TN", "type": "Output", "function": "Output 0T − / LVCMOS" }, { "number": 13, "name": "VDDIN", "type": "Power", "function": "Analog/input supply" }, { "number": 46, "name": "VDD", "type": "Power", "function": "PLL digital supply" }, { "number": 60, "name": "VDD", "type": "Power", "function": "PLL digital supply" }, { "number": 22, "name": "VDDO0B", "type": "Power", "function": "Output bank 0B supply" }, { "number": 29, "name": "VDDO1", "type": "Power", "function": "Output bank 1 supply" }, { "number": 33, "name": "VDDO2", "type": "Power", "function": "Output bank 2 supply" }, { "number": 36, "name": "VDDO3", "type": "Power", "function": "Output bank 3 supply" }, { "number": 43, "name": "VDDO5", "type": "Power", "function": "Output bank 5 supply" }, { "number": 49, "name": "VDDO6", "type": "Power", "function": "Output bank 6 supply" }, { "number": 52, "name": "VDDO7", "type": "Power", "function": "Output bank 7 supply" }, { "number": 57, "name": "VDDO0T", "type": "Power", "function": "Output bank 0T supply" }, { "number": 12, "name": "INTRB", "type": "Output", "function": "Active‑LOW aggregated sticky notify" }, { "number": 11, "name": "OEB", "type": "Input", "function": "Output disable (HIGH)" }, { "number": 6, "name": "RSTB", "type": "Input", "function": "Reset (active‑LOW); on‑chip 25 kΩ pull‑up to VDDIO" }, { "number": 18, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI SDI" }, { "number": 16, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI SCLK" }, { "number": 19, "name": "CSB/A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "SDO/A1", "type": "I/O", "function": "SPI SDO / I²C A1" }, { "number": 39, "name": "I2C1_SPI0", "type": "Input", "function": "Serial interface select: 1=I²C, 0=SPI" }, { "number": -1, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "storage_temperature_C": { "min": -55, "max": 150 }, "junction_temperature_C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V": 2000, "ESD_CDM_V": 750, "latchup_mA": 100, "MSL": 3 }, "package": { "options": [ "64‑QFN, 9×9 mm" ], "notes": [ "Integrated MEMS resonator (no external crystal required)", "Use recommended AC/DC terminations per output standard; LVDS/LVDS‑Boost preferred for AC‑coupled", "RSTB, FLEXIO inputs, I²C/SPI inputs at 1.8 V require series resistor (≈4.7 kΩ) if driving from 2.5/3.3 V" ] }, "ordering_information": { "example": "SiT95147 A I - X Y Y Y Y Y - T", "fields": { "family": "SiT95147", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X/Y characters = pre‑programmed startup config ID", "packaging": { "T": "Tape \u0026 Reel (various ku options)" } } } }, { "product_name": "SiT95148", "product_type": "Cascade ClkSoC – High‑Performance 11‑output MEMS Jitter Cleaner, Clock Synchronizer (64‑QFN 9×9 mm)", "overview": { "description": "Single‑chip MEMS jitter cleaner/clock synchronizer with integrated ApexMEMS® resonator, quad fractional‑N PLLs and up to 11 differential (or 22 LVCMOS) low‑jitter outputs. Eliminates external crystal, simplifies design, supports flexible input→output translation (8 kHz to 2.1 GHz).", "features": [ "Quad fractional‑N PLLs with integrated VCO and loop filter; typ 93 fs RMS (4‑16A) for SerDes; 127 fs RMS (12 k–20 M) example", "11 differential or 22 LVCMOS outputs; individually programmable format: LVPECL, LVPECL2, LVDS, LVDS‑Boost, HCSL, CML, or LVCMOS", "Output frequency support: differential 8 kHz–2.1 GHz; LVCMOS 1 Hz–250 MHz; 1 Hz–2.1 GHz available on OUT0", "Input support: differential 8 kHz–2.1 GHz; LVCMOS 8 kHz–250 MHz; min slew 400 V/µs", "Programmable PLL bandwidth 1 mHz–4 kHz; jitter peaking ≤0.1 dB (SONET)", "Programmable output delay control (35 ps step; ~7.5 ns range); cross‑PLL phase sync ±250 ps", "DCO mode via I²C/SPI with 0.005 ppb resolution; ±100 ppm max step", "Zero‑Delay Mode on any PLL (typ ~100 ps input→output delay; ~1 ps/°C temperature variation)", "Indicators: Clock Loss (2/4/8/16 pulses), Lock Loss (±0.2…±4000 ppm), Fine/Coarse Frequency Drift on FLEXIO/INTRB", "Two OTP banks on slaves + in‑system I²C/SPI configuration; factory pre‑program option", "Translation jitter example: ~128 fs RMS @ 156.25 MHz, FIN=10 MHz, BW=100 Hz" ], "applications": [ "Clock tree consolidation (replace XOs/buffers)", "Low‑jitter frequency translation \u0026 generation", "10G/100G/400G Ethernet, IEEE‑1588/PTP, SyncE", "FPGA/processor/memory clocking; servers/storage/datacenter", "OTN, test \u0026 measurement, broadcast video" ] }, "electrical_characteristics": { "inputs": { "count_diff": 4, "count_single_ended": 4, "frequency_range": { "differential_MHz_min": 0.008, "differential_MHz_max": 2100, "single_ended_MHz_min": 0.008, "single_ended_MHz_max": 250 }, "swing_requirements_mVpp": { "lt_400MHz": 100, "400to750MHz": 225, "gt_750MHz": 350 }, "single_ended_ac_mVpp": { "min": 500, "max": 3600 }, "slew_rate_min_V_per_us": 400, "duty_cycle_percent": [ 40, 60 ] }, "outputs": { "count_diff": 11, "count_lvcmos_pairs": 22, "frequency_range": { "diff_Hz_min": 8000, "diff_Hz_max": 2100000000, "hcsL_Hz_max": 700000000, "lvcmos_Hz_min": 1, "lvcmos_Hz_max": 250000000, "out0_special_min_Hz": 1, "out0_special_max_Hz": 2100000000 }, "pll_loop_bandwidth_Hz": 4000, "duty_cycle_percent": [ 45, 55 ], "rise_fall_time_limits": { "lvcmos_ns_max": { "1p8V": 2.0, "2p5V": 1.5, "3p3V": 1.2 }, "diff_ps_max": 350 }, "phase": { "output_delay_step_ps": 35, "output_delay_range_ns": 7.5, "cross_pll_sync_ps_max": 250 }, "standards": [ "LVPECL", "LVPECL2", "LVDS", "LVDS-Boost", "HCSL", "CML", "LVCMOS" ] }, "jitter": { "rms_fs_typ_4_16A": 93, "rms_fs_typ_12k_20M": 127, "rms_fs_typ_4_20_at_312p5MHz": 62, "close_in_phase_noise_dBc_per_Hz_typ_at_122p88MHz": { "10Hz": -91, "100Hz": -113, "1kHz": -130, "10kHz": -138 } }, "psrr_dBc_typ": { "VDD_3p3V": -96, "VDD_2p5V": -90, "VDD_1p8V": -75, "VDDIN": -70, "VDDO": -80 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "dco": { "resolution_ppb": 0.005, "max_step_ppm": 100 }, "holdover": { "frequency_stability_ppm_max": 45, "aging_10yr_ppm_typ": 2 }, "io_logic": { "i2c_slave_default_address": "0x69", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20 } }, "pins": [ { "number": 63, "name": "IN0P", "type": "Input", "function": "True input for IN0 diff / LVCMOS" }, { "number": 64, "name": "IN0N", "type": "Input", "function": "Complement for IN0 diff; cap‑to‑GND for LVCMOS" }, { "number": 1, "name": "IN1P", "type": "Input", "function": "True input for IN1 diff / LVCMOS" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Complement for IN1 diff; cap‑to‑GND for LVCMOS" }, { "number": 14, "name": "IN2P", "type": "Input", "function": "True input for IN2 diff / LVCMOS" }, { "number": 15, "name": "IN2N", "type": "Input", "function": "Complement for IN2 diff; cap‑to‑GND for LVCMOS" }, { "number": 61, "name": "IN3P", "type": "Input", "function": "True input for IN3 diff / LVCMOS / ZDB feedback" }, { "number": 62, "name": "IN3N", "type": "Input", "function": "Complement for IN3 diff; cap‑to‑GND for LVCMOS / ZDB feedback" }, { "number": 21, "name": "OUT0BP", "type": "Output", "function": "Output 0B + / LVCMOS" }, { "number": 20, "name": "OUT0BN", "type": "Output", "function": "Output 0B − / LVCMOS" }, { "number": 24, "name": "OUT1BP", "type": "Output", "function": "Output 1B + / LVCMOS" }, { "number": 23, "name": "OUT1BN", "type": "Output", "function": "Output 1B − / LVCMOS" }, { "number": 28, "name": "OUT0P", "type": "Output", "function": "Output 0 + / LVCMOS" }, { "number": 27, "name": "OUT0N", "type": "Output", "function": "Output 0 − / LVCMOS" }, { "number": 31, "name": "OUT1P", "type": "Output", "function": "Output 1 + / LVCMOS" }, { "number": 30, "name": "OUT1N", "type": "Output", "function": "Output 1 − / LVCMOS" }, { "number": 35, "name": "OUT2P", "type": "Output", "function": "Output 2 + / LVCMOS" }, { "number": 34, "name": "OUT2N", "type": "Output", "function": "Output 2 − / LVCMOS" }, { "number": 38, "name": "OUT3P", "type": "Output", "function": "Output 3 + / LVCMOS" }, { "number": 37, "name": "OUT3N", "type": "Output", "function": "Output 3 − / LVCMOS" }, { "number": 42, "name": "OUT4P", "type": "Output", "function": "Output 4 + / LVCMOS" }, { "number": 41, "name": "OUT4N", "type": "Output", "function": "Output 4 − / LVCMOS" }, { "number": 45, "name": "OUT5P", "type": "Output", "function": "Output 5 + / LVCMOS" }, { "number": 44, "name": "OUT5N", "type": "Output", "function": "Output 5 − / LVCMOS" }, { "number": 51, "name": "OUT6P", "type": "Output", "function": "Output 6 + / LVCMOS" }, { "number": 50, "name": "OUT6N", "type": "Output", "function": "Output 6 − / LVCMOS" }, { "number": 54, "name": "OUT7P", "type": "Output", "function": "Output 7 + / LVCMOS" }, { "number": 53, "name": "OUT7N", "type": "Output", "function": "Output 7 − / LVCMOS" }, { "number": 59, "name": "OUT0TP", "type": "Output", "function": "Output 0T + / LVCMOS" }, { "number": 58, "name": "OUT0TN", "type": "Output", "function": "Output 0T − / LVCMOS" }, { "number": 13, "name": "VDDIN", "type": "Power", "function": "Analog/input supply" }, { "number": 46, "name": "VDD", "type": "Power", "function": "PLL digital supply" }, { "number": 60, "name": "VDD", "type": "Power", "function": "PLL digital supply" }, { "number": 22, "name": "VDDO1B", "type": "Power", "function": "Output bank 0B and 1B supplies" }, { "number": 26, "name": "VDDO0", "type": "Power", "function": "Output bank 0 supply" }, { "number": 29, "name": "VDDO1", "type": "Power", "function": "Output bank 1 supply" }, { "number": 33, "name": "VDDO2", "type": "Power", "function": "Output bank 2 supply" }, { "number": 36, "name": "VDDO3", "type": "Power", "function": "Output bank 3 supply" }, { "number": 40, "name": "VDDO4", "type": "Power", "function": "Output bank 4 supply" }, { "number": 43, "name": "VDDO5", "type": "Power", "function": "Output bank 5 supply" }, { "number": 49, "name": "VDDO6", "type": "Power", "function": "Output bank 6 supply" }, { "number": 52, "name": "VDDO7", "type": "Power", "function": "Output bank 7 supply" }, { "number": 57, "name": "VDDO0T", "type": "Power", "function": "Output bank 0T supply" }, { "number": 12, "name": "INTRB", "type": "Output", "function": "Active‑LOW aggregated sticky notify" }, { "number": 11, "name": "OEB", "type": "Input", "function": "Output disable (HIGH)" }, { "number": 6, "name": "RSTB", "type": "Input", "function": "Reset (active‑LOW); on‑chip 25 kΩ pull‑up to VDDIO" }, { "number": 18, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI SDI" }, { "number": 16, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI SCLK" }, { "number": 19, "name": "CSB/A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "SDO/A1", "type": "I/O", "function": "SPI SDO / I²C A1" }, { "number": 39, "name": "I2C1_SPI0", "type": "Input", "function": "Serial interface select: 1=I²C, 0=SPI" }, { "number": -1, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "storage_temperature_C": { "min": -55, "max": 150 }, "junction_temperature_C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V": 2000, "ESD_CDM_V": 750, "latchup_mA": 100, "MSL": 3 }, "package": { "options": [ "64‑QFN, 9×9 mm" ], "notes": [ "Integrated MEMS resonator (no external crystal required)", "Use recommended AC/DC terminations per output standard; LVDS/LVDS‑Boost preferred for AC‑coupled", "RSTB, FLEXIO inputs, I²C/SPI inputs at 1.8 V require series resistor (≈4.7 kΩ) if driving from 2.5/3.3 V" ] }, "ordering_information": { "example": "SiT95148 A I - X Y Y Y Y Y - T", "fields": { "family": "SiT95148", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X/Y characters = pre‑programmed startup config ID", "packaging": { "T": "Tape \u0026 Reel (various ku options)" } } } }, { "product_name": "SiT95210", "product_type": "Ultra Low Jitter, Quad PLL, Programmable Frequency, 4‑Output Clock Generator (44‑QFN 7×7 mm)", "overview": { "description": "Quad fractional frequency‑translation clock generator with 4 independent PLLs, 4 differential (8 single‑ended) inputs, and 4 clock outputs. Flexible input→output muxing, JESD204B/C support, optional external EEPROM, and on‑chip OTP.", "features": [ "Sub‑70 fs typical RMS integrated jitter (12 kHz–20 MHz); ≈85 fs with 48 MHz crystal", "4 Diff / 8 SE inputs; 4 outputs selectable from any PLL", "Input 200 kHz–2.1 GHz (diff), 200 kHz–250 MHz (SE); Output 0.5 Hz–2.94912 GHz", "Differential outputs continuous to 800 MHz; specific 61.44 MHz multiples up to 2.94912 GHz", "Fully integrated design (no external loop components); flexible input/output mux", "DCO frequency control down to 0.001 ppt; phase DCO \u003c 1 ps resolution", "Internal/External Zero‑Delay Buffer (ZDB) support; input→output delay variation \u003c 0.5 ns (internal)", "SYSREF (continuous/pulser) and SYNCB modes for JESD204B/C", "Extensive fault monitors: clock loss, frequency drift (fine/coarse), lock loss, XO loss", "I²C/SPI programmable; optional external I²C EEPROM configuration; OTP NVM" ], "applications": [ "Carrier Ethernet / SyncE / IEEE‑1588", "OTN equipment, microwave backhaul", "Gigabit/10G/25G/100G Ethernet, SONET/SDH", "Wireless infrastructure, small cells", "Network line cards, data center/storage", "Test \u0026 instrumentation, broadcast video" ] }, "electrical_characteristics": { "supplies": { "VDDIN_V": { "min": 2.97, "typ": 3.3, "max": 3.63 }, "VDD_V": { "min": 1.71, "typ": 1.8, "max": 1.89 }, "VDDO_V": [ { "min": 1.71, "typ": 1.8, "max": 1.89 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 2.97, "typ": 3.3, "max": 3.63 } ], "power_dissipation_W_typ": 1.2 }, "inputs": { "count_diff": 4, "count_single_ended": 8, "frequency_range": { "differential_min_Hz": 200000, "differential_max_Hz": 2100000000, "single_ended_min_Hz": 200000, "single_ended_max_Hz": 250000000, "pll_phase_detector_max_Hz": 12500000 }, "swing_requirements_mVpp_diff": { "\u003c400MHz_min": 100, "400–750MHz_min": 225, "\u003e750MHz_min": 350 }, "single_ended_ac_mVpp": { "min": 500, "max": 3600 }, "slew_rate_min_V_per_µs": 400, "duty_cycle_percent": [ 40, 60 ] }, "outputs": { "count_diff": 4, "count_lvcmos_pairs": 8, "frequency_range": { "diff_continuous_min_Hz": 0.5, "diff_continuous_max_Hz": 800000000, "diff_selective_high_Hz": [ 921600000, 1228800000, 1574560000, 1843200000, 1966080000, 2457600000, 2949120000 ], "lvcmos_min_Hz": 0.5, "lvcmos_max_Hz": 250000000, "all_standards_max_Hz": 2949120000 }, "rise_fall_time_limits": { "lvcmos_ns_max": { "1.8V": 2.0, "2.5V": 1.5, "3.3V": 1.2 }, "diff_ps_max": 350 }, "duty_cycle_percent": [ 45, 55 ], "phase": { "output_delay_step_ps": 35, "output_skew_ps": [ -50, 50 ], "input_phase_shift_resolution_ps": 1 }, "standards": { "LVDS": { "diff_peak_mV_steps": [ 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 ] }, "HCSL": { "diff_peak_mV_steps": [ 500, 550, 600, 650, 700, 750, 800, 900, 1000 ] }, "CML": { "diff_peak_mV_steps": [ 50, 100, 150, 200, 250, 300, 350, 400, 500, 600 ] }, "LVPECL": { "diff_peak_mV_steps": [ 500, 540, 580, 620, 660, 680, 700, 720, 900 ] }, "LVCMOS": { "max_frequency_Hz": 250000000 } } }, "jitter": { "rms_fs_typ_12k–20M": 70, "rms_fs_typ_with_48MHz_xtal_fs": 85, "test_condition": "FOUT=156.25 MHz; ext. 76.8 MHz MEMS for 70 fs" }, "psrr_dBc_typ": { "VDD": -80, "VDDIN": -100, "VDDO": -90 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "dco": { "frequency_step_resolution_ppt": 0.001, "note": "Per‑step resolution; larger steps up to 100 ppm available" }, "io_logic": { "i2c_default_address": "0x69", "i2c_addressing": "7‑bit; A1 from SDO, A0 from CSB; optional A2 via GPIO latch", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20, "interface_select_pin": { "name": "I2C1_SPI0", "I²C": 1, "SPI": 0 }, "powerup_serial_ready_ms": 10 } }, "pins": [ { "number": 1, "name": "IN1P", "type": "Input", "function": "Clock input + (diff/SE)" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Clock input − (diff/SE)" }, { "number": 3, "name": "GPIO0/IN_SEL0", "type": "I/O", "function": "Manual input clock select bit 0 / GPIO" }, { "number": 4, "name": "X1G", "type": "GND", "function": "Crystal ground" }, { "number": 5, "name": "X1", "type": "Input", "function": "Crystal / external XO input" }, { "number": 6, "name": "X2", "type": "Output", "function": "Crystal pin (leave open with external XO)" }, { "number": 7, "name": "X2G", "type": "GND", "function": "Crystal ground" }, { "number": 8, "name": "VDDIN", "type": "Power", "function": "Input/analog supply" }, { "number": 9, "name": "VDDIN", "type": "Power", "function": "Input/analog supply" }, { "number": 10, "name": "IN2P", "type": "Input", "function": "Clock input + (diff/SE)" }, { "number": 11, "name": "IN2N", "type": "Input", "function": "Clock input − (diff/SE)" }, { "number": 12, "name": "GPIO1/OEb", "type": "I/O", "function": "Output disable (HIGH disables) / GPIO" }, { "number": 13, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI SDI" }, { "number": 14, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI SCLK" }, { "number": 15, "name": "SDO_A1", "type": "Output", "function": "SPI SDO / I²C A1" }, { "number": 16, "name": "CSB_A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "RSTB", "type": "Input", "function": "Reset, active‑LOW" }, { "number": 18, "name": "VDDO0", "type": "Power", "function": "OUT0 driver supply" }, { "number": 19, "name": "OUT0N", "type": "Output", "function": "Clock output 0 − / LVCMOS" }, { "number": 20, "name": "OUT0P", "type": "Output", "function": "Clock output 0 + / LVCMOS" }, { "number": 21, "name": "VDD", "type": "Power", "function": "Core/PLL supply" }, { "number": 22, "name": "NC", "type": "NC", "function": "No connect" }, { "number": 23, "name": "VDDO1", "type": "Power", "function": "OUT1 driver supply" }, { "number": 24, "name": "OUT1N", "type": "Output", "function": "Clock output 1 − / LVCMOS" }, { "number": 25, "name": "OUT1P", "type": "Output", "function": "Clock output 1 + / LVCMOS" }, { "number": 26, "name": "VDDS", "type": "Power", "function": "GPIO supply for pins 27/28" }, { "number": 27, "name": "GPIO2/LOLb", "type": "I/O", "function": "Loss‑of‑lock (active‑LOW) / GPIO" }, { "number": 28, "name": "GPIO3/LOS_XOb", "type": "I/O", "function": "XO loss status / GPIO" }, { "number": 29, "name": "VDDO2", "type": "Power", "function": "OUT2 driver supply" }, { "number": 30, "name": "OUT2N", "type": "Output", "function": "Clock output 2 − / LVCMOS" }, { "number": 31, "name": "OUT2P", "type": "Output", "function": "Clock output 2 + / LVCMOS" }, { "number": 32, "name": "VDD", "type": "Power", "function": "Core/PLL supply" }, { "number": 33, "name": "INTRb", "type": "I/O", "function": "Aggregated notify (active‑LOW)" }, { "number": 34, "name": "VDDO3", "type": "Power", "function": "OUT3 driver supply" }, { "number": 35, "name": "OUT3N", "type": "Output", "function": "Clock output 3 − / LVCMOS" }, { "number": 36, "name": "OUT3P", "type": "Output", "function": "Clock output 3 + / LVCMOS" }, { "number": 37, "name": "GPIO5/IN_SEL1", "type": "I/O", "function": "Manual input clock select bit 1 / GPIO" }, { "number": 38, "name": "I2C1_SPI0", "type": "Input", "function": "Serial mode select (1=I²C, 0=SPI)" }, { "number": 39, "name": "VDD", "type": "Power", "function": "Core/PLL supply" }, { "number": 40, "name": "VDD", "type": "Power", "function": "Core/PLL supply" }, { "number": 41, "name": "IN3P", "type": "Input", "function": "Clock input + (diff/SE)" }, { "number": 42, "name": "IN3N", "type": "Input", "function": "Clock input − (diff/SE)" }, { "number": 43, "name": "IN0P", "type": "Input", "function": "Clock input + (diff/SE)" }, { "number": 44, "name": "IN0N", "type": "Input", "function": "Clock input − (diff/SE)" }, { "number": -1, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "xo_input_max_V": 1.8, "storage_temperature_°C": { "min": -55, "max": 150 }, "programming_temperature_°C": { "min": 25, "max": 85 }, "junction_temperature_°C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V_max": 2000, "ESD_CDM_V_max": 500, "latchup_mA_min": 100, "MSL": 3 }, "package": { "options": [ "44‑QFN, 7×7 mm" ], "notes": [ "Internal 100 Ω LVDS termination option; prefer LVDS for AC‑coupled links", "Outputs default Hi‑Z after reset; OEb HIGH disables outputs", "Hold RSTB LOW until supplies ≥ 90 % of final value; serial interface ready ≈ 10 ms after" ] }, "ordering_information": { "example": "SiT95210 A I - X Y Y Y Y Y - P", "fields": { "family": "SiT95210", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X = A (blank) / B (pre‑configured), Y = 0–9, A–Z custom ID", "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } } }, { "product_name": "SiT95314", "product_type": "Quad PLL Frequency Translator / Jitter Cleaner / Network \u0026 Port Synchronizer (44-QFN 7×7 mm)", "overview": { "description": "Quad fractional-N PLL clock IC that cleans jitter, translates frequency, and synchronizes network/ports. Supports 4 differential (8 single-ended) inputs shared across 4 PLLs and 4 routable differential outputs (or 8 LVCMOS). Optional external EEPROM boot; OTP; I²C/SPI configuration.", "features": [ "Ultra-high performance PLLs; ~70 fs typ RMS jitter (12 kHz–20 MHz) at 156.25 MHz with MEMS XO; ~85 fs with 48 MHz crystal", "Input support: 4 differential / 8 single-ended; internal dividers ensure PLL phase-detector ≤ 12.5 MHz", "Outputs: continuous 0.5 Hz–800 MHz; selected multiples up to 2.94912 GHz; LVCMOS up to 250 MHz", "Programmable loop bandwidth: 0.09 mHz to 4 kHz; excellent close-in phase noise at 122.88 MHz", "Hitless switching: Phase Build-Out (≤±25 ps), Phase Propagation (programmable slope), Frequency Ramp", "Zero-Delay Buffer modes: internal (≤±0.5 ns I/O delay variation) and external (±100 ps window)", "JESD204B/C support: SYSREF (continuous or pulser, 1–255 pulses) and SYNCB trigger", "Fine output phase adjustment (35 ps steps); input phase shift (≈1 ps steps)", "Fault monitors: clock loss, fine/coarse frequency drift, lock loss (±0.05 ppb to ±4000 ppm), XO loss", "I²C master for EEPROM boot (100/400 kHz), I²C/SPI slave control, GPIO latching at reset" ], "applications": [ "Carrier Ethernet, OTN equipment, Microwave backhaul", "Wireless infrastructure, Small cells, Network line cards", "Data center / storage, Test \u0026 instrumentation, Broadcast video", "JESD204B/C data-converter clocking" ] }, "electrical_characteristics": { "inputs": { "count_diff": 4, "count_single_ended": 8, "frequency_range_Hz": { "differential_min": 8000, "differential_max": 2100000000, "single_ended_min": 8000, "single_ended_max": 250000000 }, "pll_phase_detector_max_Hz": 12500000, "swing_requirements_mVpp": { "lt_400MHz": 100, "400to750MHz": 225, "gt_750MHz": 350 }, "slew_rate_min_V_per_us": 400, "duty_cycle_percent": [ 40, 60 ] }, "reference_clock_X1": { "frequency_MHz": { "overall_min": 25, "overall_max": 192, "best_jitter_min": 48, "best_jitter_max": 192 }, "single_ended_swing_mVpp": { "min": 365, "max": 2000 } }, "outputs": { "count_diff": 4, "count_lvcmos_pairs": 8, "frequency_range_Hz": { "continuous_min": 0.5, "continuous_max": 800000000, "selective_high_min": 921600000, "selective_high_max": 2949120000, "lvcmos_min": 0.5, "lvcmos_max": 250000000 }, "rise_fall_time_ps_max": 350, "duty_cycle_percent": [ 45, 55 ], "phase_adjust_ps": { "output_step": 35, "input_step": 1 } }, "jitter": { "rms_phase_jitter_fs_typ_12k_20M": 70, "rms_phase_jitter_fs_with_48MHz_xtal": 85, "phase_noise_dBc_per_Hz_typ_at_122p88MHz": { "100Hz": -116, "1kHz": -127, "10kHz": -136, "100kHz": -145, "1MHz": -155, "10MHz": -163 } }, "loop_bandwidth_Hz": { "min": 9E-05, "max": 4000 }, "dco": { "resolution_ppt": 0.001, "inner_loop_fraction_bits": 48, "outer_loop_fraction_bits": 48, "outer_loop_integer_bits": 24 }, "supplies": { "VDDIN_V": { "min": 3.0, "max": 3.6 }, "VDD_V": { "min": 1.71, "max": 1.89 }, "VDDO_V_options": [ { "min": 1.71, "max": 1.89 }, { "min": 2.375, "max": 2.625 }, { "min": 2.97, "max": 3.63 } ], "power_typ_W_example": 1.2 }, "psrr_dBc_typ": { "VDDIN": -100, "VDD": -80, "VDDO": -90 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "io_logic": { "i2c_slave_default_address": "0x69", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20, "gpio_latching_supported": true } }, "pins": [ { "number": 1, "name": "IN1P", "type": "Input", "function": "Differential clock + / Single-ended input" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Differential clock − / Single-ended input" }, { "number": 5, "name": "X1", "type": "Input", "function": "Reference clock / crystal input (25–192 MHz)" }, { "number": 6, "name": "X2", "type": "Output", "function": "Crystal feedback output; leave open with XO input" }, { "number": 12, "name": "GPIO1/OEb", "type": "I/O", "function": "Active-HIGH: disable all outputs; configurable GPIO" }, { "number": 13, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI data" }, { "number": 14, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI clock" }, { "number": 15, "name": "SDO_A1", "type": "Output", "function": "SPI SDO / I²C A1" }, { "number": 16, "name": "CSB_A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "RSTB", "type": "Input", "function": "Active-LOW reset; release after supplies \u003e90%" }, { "number": 20, "name": "OUT0P", "type": "Output", "function": "Clock + (diff) / LVCMOS" }, { "number": 19, "name": "OUT0N", "type": "Output", "function": "Clock − (diff) / LVCMOS" }, { "number": 25, "name": "OUT1P", "type": "Output", "function": "Clock + (diff) / LVCMOS" }, { "number": 24, "name": "OUT1N", "type": "Output", "function": "Clock − (diff) / LVCMOS" }, { "number": 31, "name": "OUT2P", "type": "Output", "function": "Clock + (diff) / LVCMOS" }, { "number": 30, "name": "OUT2N", "type": "Output", "function": "Clock − (diff) / LVCMOS" }, { "number": 36, "name": "OUT3P", "type": "Output", "function": "Clock + (diff) / LVCMOS" }, { "number": 35, "name": "OUT3N", "type": "Output", "function": "Clock − (diff) / LVCMOS" }, { "number": 18, "name": "VDDO0", "type": "Power", "function": "Output-bank supply for OUT0" }, { "number": 23, "name": "VDDO1", "type": "Power", "function": "Output-bank supply for OUT1" }, { "number": 29, "name": "VDDO2", "type": "Power", "function": "Output-bank supply for OUT2" }, { "number": 34, "name": "VDDO3", "type": "Power", "function": "Output-bank supply for OUT3" }, { "number": 8, "name": "VDDIN", "type": "Power", "function": "Input/XTAL analog supply (3.0–3.6 V)" }, { "number": 21, "name": "VDD", "type": "Power", "function": "PLL digital supply (1.71–1.89 V)" }, { "number": 33, "name": "INTRb", "type": "Output", "function": "Active-LOW aggregated alarm (sticky notify)" }, { "number": 38, "name": "I2C1_SPI0", "type": "Input", "function": "Serial mode select: 1=I²C, 0=SPI" }, { "number": 0, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "xo_pin_voltage_V": { "min": -0.5, "max": 1.8 }, "storage_temperature_C": { "min": -55, "max": 150 }, "junction_temperature_C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V": 2000, "ESD_CDM_V": 500, "latchup_mA": 100, "MSL": 3 }, "package": { "options": [ "44-QFN, 7×7 mm" ], "notes": [ "Hold RSTB LOW until supplies reach ≥90% of target; obey GPIO latch timing if used", "Route X1/X2 short and close to pins; support XO or crystal per datasheet", "Supports internal 100 Ω LVDS termination option" ] }, "ordering_information": { "example": "SiT95314 A I - X Y Y Y Y Y - P", "fields": { "family": "SiT95314", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X/Y characters tie to pre-programmed startup configuration", "packaging": { "N": "500 u Tape \u0026 Reel", "P": "4 ku Tape \u0026 Reel" } } } }, { "product_name": "SiT95316", "product_type": "Quad PLL, 12‑output Network Synchronizer / Jitter Cleaner (64‑QFN 9×9 mm)", "overview": { "description": "Quad fractional‑N DPLL network synchronizer providing flexible input→output frequency translation and up to 12 differential (or 24 LVCMOS) low‑jitter outputs. Fully programmable via I²C/SPI or OTP; supports 1 PPS I/O, JESD204B/C, and integrated wander attenuation.", "features": [ "Ultra‑high performance DPLLs; ~70 fs typical RMS integrated jitter (12 k–20 M)", "Inputs: up to 4 differential or 8 single‑ended; outputs: up to 12 differential / 24 LVCMOS", "Input frequency 0.5 Hz–2.1 GHz (differential); output frequency 0.5 Hz–2.94912 GHz", "Fully flexible input/output multiplexing; outputs can source from any PLL", "1 PPS input/output with \u003c20 s lock time; internal ZDB mode with \u003c0.5 ns I/O delay variation", "Programmable wander attenuation loop BW down to 0.09 mHz; best‑in‑class hitless switching (PBO \u003c25 ps, phase propagation \u0026 frequency ramp with programmable slopes)", "DCO: frequency control down to 0.001 ppt on all outputs; phase control \u003c1 ps resolution", "Supports external EEPROM; two‑time programmable NVM (OTP) option", "JESD204B/C clocking support; outputs can be phase‑aligned on sync pulse" ], "applications": [ "Carrier Ethernet, SyncE / IEEE‑1588 PTP", "OTN equipment, microwave backhaul", "Data center / storage, network line cards, small cells", "Gigabit/10G/25G/100G Ethernet, SONET/SDH", "Test \u0026 measurement, broadcast video" ] }, "electrical_characteristics": { "inputs": { "count_diff": 4, "count_single_ended": 8, "frequency_range": { "differential_MHz_min": 0.0005, "differential_MHz_max": 2100, "single_ended_MHz_min": 0.0005, "single_ended_MHz_max": 250 }, "swing_requirements_mVpp": { "lt_400MHz": 100, "400to750MHz": 225, "gt_750MHz": 350 }, "single_ended_ac_mVpp": { "min": 500, "max": 3600 }, "slew_rate_min_V_per_us": 400, "duty_cycle_percent": [ 40, 60 ] }, "outputs": { "count_diff": 12, "count_lvcmos_pairs": 24, "frequency_range": { "diff_Hz_min": 0.5, "diff_Hz_max": 2949120000, "hcsL_Hz_max": 700000000, "lvcmos_Hz_min": 0.5, "lvcmos_Hz_max": 250000000, "out0_special_min_Hz": 0.5, "out0_special_max_Hz": 2949120000 }, "pll_loop_bandwidth_Hz": 4000, "duty_cycle_percent": [ 45, 55 ], "rise_fall_time_limits": { "lvcmos_ns_max": { "1p8V": 2.0, "2p5V": 1.5, "3p3V": 1.2 }, "diff_ps_max": 350 }, "phase": { "output_delay_step_ps": 35, "output_delay_range_ns": 7.5, "cross_pll_sync_ps_max": 250 }, "standards": [ "LVPECL", "CML", "HCSL", "LVDS", "LVCMOS" ] }, "jitter": { "rms_fs_typ_12k_20M": 70, "rms_fs_typ_4M_20M": 85 }, "psrr_dBc_typ": { "VDD_3p3V": -96, "VDD_2p5V": -90, "VDD_1p8V": -75, "VDDIN": -70, "VDDO": -80 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "dco": { "resolution_ppb": 1E-06, "max_step_ppm": 100 }, "holdover": { "frequency_stability_ppm_max": 45, "aging_10yr_ppm_typ": 2 }, "io_logic": { "i2c_slave_default_address": "0x69", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20 } }, "pins": [ { "number": 63, "name": "IN0P", "type": "Input", "function": "True input for IN0 diff / LVCMOS" }, { "number": 64, "name": "IN0N", "type": "Input", "function": "Complement for IN0 diff; cap‑to‑GND for LVCMOS" }, { "number": 1, "name": "IN1P", "type": "Input", "function": "True input for IN1 diff / LVCMOS" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Complement for IN1 diff; cap‑to‑GND for LVCMOS" }, { "number": 14, "name": "IN2P", "type": "Input", "function": "True input for IN2 diff / LVCMOS" }, { "number": 15, "name": "IN2N", "type": "Input", "function": "Complement for IN2 diff; cap‑to‑GND for LVCMOS" }, { "number": 61, "name": "IN3P", "type": "Input", "function": "True input for IN3 diff / LVCMOS / 1PPS" }, { "number": 62, "name": "IN3N", "type": "Input", "function": "Complement for IN3 diff; cap‑to‑GND for LVCMOS / 1PPS" }, { "number": 28, "name": "OUT0P", "type": "Output", "function": "Output 0 + / LVCMOS" }, { "number": 27, "name": "OUT0N", "type": "Output", "function": "Output 0 − / LVCMOS" }, { "number": 31, "name": "OUT1P", "type": "Output", "function": "Output 1 + / LVCMOS" }, { "number": 30, "name": "OUT1N", "type": "Output", "function": "Output 1 − / LVCMOS" }, { "number": 35, "name": "OUT2P", "type": "Output", "function": "Output 2 + / LVCMOS" }, { "number": 34, "name": "OUT2N", "type": "Output", "function": "Output 2 − / LVCMOS" }, { "number": 38, "name": "OUT3P", "type": "Output", "function": "Output 3 + / LVCMOS" }, { "number": 37, "name": "OUT3N", "type": "Output", "function": "Output 3 − / LVCMOS" }, { "number": 42, "name": "OUT4P", "type": "Output", "function": "Output 4 + / LVCMOS" }, { "number": 41, "name": "OUT4N", "type": "Output", "function": "Output 4 − / LVCMOS" }, { "number": 45, "name": "OUT5P", "type": "Output", "function": "Output 5 + / LVCMOS" }, { "number": 44, "name": "OUT5N", "type": "Output", "function": "Output 5 − / LVCMOS" }, { "number": 51, "name": "OUT6P", "type": "Output", "function": "Output 6 + / LVCMOS" }, { "number": 50, "name": "OUT6N", "type": "Output", "function": "Output 6 − / LVCMOS" }, { "number": 54, "name": "OUT7P", "type": "Output", "function": "Output 7 + / LVCMOS" }, { "number": 53, "name": "OUT7N", "type": "Output", "function": "Output 7 − / LVCMOS" }, { "number": 13, "name": "VDDIN", "type": "Power", "function": "Analog/input supply" }, { "number": 46, "name": "VDD", "type": "Power", "function": "Core/PLL digital supply" }, { "number": 60, "name": "VDD", "type": "Power", "function": "Core/PLL digital supply" }, { "number": 26, "name": "VDDO0", "type": "Power", "function": "Output bank 0 supply" }, { "number": 29, "name": "VDDO1", "type": "Power", "function": "Output bank 1 supply" }, { "number": 33, "name": "VDDO2", "type": "Power", "function": "Output bank 2 supply" }, { "number": 36, "name": "VDDO3", "type": "Power", "function": "Output bank 3 supply" }, { "number": 40, "name": "VDDO4", "type": "Power", "function": "Output bank 4 supply" }, { "number": 43, "name": "VDDO5", "type": "Power", "function": "Output bank 5 supply" }, { "number": 49, "name": "VDDO6", "type": "Power", "function": "Output bank 6 supply" }, { "number": 52, "name": "VDDO7", "type": "Power", "function": "Output bank 7 supply" }, { "number": 12, "name": "INTRB", "type": "Output", "function": "Active‑LOW aggregated notify" }, { "number": 11, "name": "OEB", "type": "Input", "function": "Output enable (HIGH disables)" }, { "number": 6, "name": "RSTB", "type": "Input", "function": "Reset (active‑LOW); on‑chip pull‑up" }, { "number": 18, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI SDI" }, { "number": 16, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI SCLK" }, { "number": 19, "name": "CSB/A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "SDO/A1", "type": "I/O", "function": "SPI SDO / I²C A1" }, { "number": 39, "name": "I2C1_SPI0", "type": "Input", "function": "Serial interface select (1=I²C)" }, { "number": -1, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "storage_temperature_C": { "min": -55, "max": 150 }, "junction_temperature_C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V": 2000, "ESD_CDM_V": 750, "latchup_mA": 100, "MSL": 3 }, "package": { "options": [ "64‑QFN, 9×9 mm" ], "notes": [ "Integrated MEMS resonator reference architecture (no external crystal required for on-chip reference); device also supports external XO inputs", "Use recommended AC/DC terminations per output standard; LVDS/LVDS‑Boost/LVPECL preferred for AC‑coupled", "RSTB / FLEXIO / I²C/SPI at 1.8 V: use series resistor (~4.7 kΩ) if driven from 2.5/3.3 V logic" ] }, "ordering_information": { "example": "SiT95316 A I - X Y Y Y Y Y - T", "fields": { "family": "SiT95316", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X/Y characters = pre‑programmed startup config ID", "packaging": { "T": "Tape \u0026 Reel" } } } }, { "product_name": "SiT95317", "product_type": "Quad PLL, 8‑output Network Synchronizer / Jitter Cleaner (64‑QFN 9×9 mm)", "overview": { "description": "Quad fractional‑N DPLL jitter cleaner and network synchronizer with flexible input→output translation and up to 8 differential (or 16 LVCMOS) low‑jitter outputs. Fully programmable via I²C/SPI or OTP; supports 1 PPS I/O, JESD204B/C, and wander attenuation.", "features": [ "Ultra‑high performance DPLLs; 70 fs typ RMS jitter (12 k–20 M), 35 fs typ (4 M–20 M)", "Inputs: up to 4 differential or 8 single‑ended; outputs: up to 8 differential / 16 LVCMOS", "Input frequency 0.5 Hz–2.1 GHz (differential); output frequency 0.5 Hz–2.94912 GHz", "Fully flexible input/output mux; outputs can source from any PLL", "1 PPS input/output with \u003c20 s lock time; internal ZDB mode with \u003c0.5 ns I/O delay variation", "Programmable wander attenuation loop BW down to 0.09 mHz; hitless switching (PBO \u003c25 ps, phase propagation \u0026 frequency ramp with programmable slopes)", "DCO: frequency control down to 0.001 ppt on all outputs; phase control \u003c1 ps resolution", "External EEPROM support; OTP option", "JESD204B/C clocking; outputs phase‑alignable via sync pulse" ], "applications": [ "Carrier Ethernet, SyncE / IEEE‑1588 PTP", "OTN equipment, microwave backhaul", "Network line cards, small cells, data center / storage", "Gigabit/10G/25G/100G Ethernet, SONET/SDH", "Test \u0026 measurement, broadcast video" ] }, "electrical_characteristics": { "inputs": { "count_diff": 4, "count_single_ended": 8, "frequency_range": { "differential_MHz_min": 0.0005, "differential_MHz_max": 2100, "single_ended_MHz_min": 0.0005, "single_ended_MHz_max": 250 }, "swing_requirements_mVpp": { "lt_400MHz": 100, "400to750MHz": 225, "gt_750MHz": 350 }, "single_ended_ac_mVpp": { "min": 500, "max": 3600 }, "slew_rate_min_V_per_us": 400, "duty_cycle_percent": [ 40, 60 ] }, "outputs": { "count_diff": 8, "count_lvcmos_pairs": 16, "frequency_range": { "diff_Hz_min": 0.5, "diff_Hz_max": 2949120000, "hcsL_Hz_max": 700000000, "lvcmos_Hz_min": 0.5, "lvcmos_Hz_max": 250000000, "out0_special_min_Hz": 0.5, "out0_special_max_Hz": 2949120000 }, "pll_loop_bandwidth_Hz": 4000, "duty_cycle_percent": [ 45, 55 ], "rise_fall_time_limits": { "lvcmos_ns_max": { "1p8V": 2.0, "2p5V": 1.5, "3p3V": 1.2 }, "diff_ps_max": 350 }, "phase": { "output_delay_step_ps": 35, "output_delay_range_ns": 7.5, "cross_pll_sync_ps_max": 250 }, "standards": [ "LVPECL", "CML", "HCSL", "LVDS", "LVCMOS" ] }, "jitter": { "rms_fs_typ_12k_20M": 70, "rms_fs_typ_4M_20M": 35 }, "psrr_dBc_typ": { "VDD_3p3V": -96, "VDD_2p5V": -90, "VDD_1p8V": -75, "VDDIN": -70, "VDDO": -80 }, "crosstalk_adjacent_outputs_dBc_typ": -75, "dco": { "resolution_ppb": 1E-06, "max_step_ppm": 100 }, "holdover": { "frequency_stability_ppm_max": 45, "aging_10yr_ppm_typ": 2 }, "io_logic": { "i2c_slave_default_address": "0x69", "i2c_speeds_kHz": [ 100, 400 ], "spi_max_MHz": 20 } }, "pins": [ { "number": 63, "name": "IN0P", "type": "Input", "function": "True input for IN0 diff / LVCMOS" }, { "number": 64, "name": "IN0N", "type": "Input", "function": "Complement for IN0 diff; cap‑to‑GND for LVCMOS" }, { "number": 1, "name": "IN1P", "type": "Input", "function": "True input for IN1 diff / LVCMOS" }, { "number": 2, "name": "IN1N", "type": "Input", "function": "Complement for IN1 diff; cap‑to‑GND for LVCMOS" }, { "number": 14, "name": "IN2P", "type": "Input", "function": "True input for IN2 diff / LVCMOS" }, { "number": 15, "name": "IN2N", "type": "Input", "function": "Complement for IN2 diff; cap‑to‑GND for LVCMOS" }, { "number": 61, "name": "IN3P", "type": "Input", "function": "True input for IN3 diff / LVCMOS / 1PPS" }, { "number": 62, "name": "IN3N", "type": "Input", "function": "Complement for IN3 diff; cap‑to‑GND for LVCMOS / 1PPS" }, { "number": 28, "name": "OUT0P", "type": "Output", "function": "Output 0 + / LVCMOS" }, { "number": 27, "name": "OUT0N", "type": "Output", "function": "Output 0 − / LVCMOS" }, { "number": 31, "name": "OUT1P", "type": "Output", "function": "Output 1 + / LVCMOS" }, { "number": 30, "name": "OUT1N", "type": "Output", "function": "Output 1 − / LVCMOS" }, { "number": 35, "name": "OUT2P", "type": "Output", "function": "Output 2 + / LVCMOS" }, { "number": 34, "name": "OUT2N", "type": "Output", "function": "Output 2 − / LVCMOS" }, { "number": 38, "name": "OUT3P", "type": "Output", "function": "Output 3 + / LVCMOS" }, { "number": 37, "name": "OUT3N", "type": "Output", "function": "Output 3 − / LVCMOS" }, { "number": 13, "name": "VDDIN", "type": "Power", "function": "Analog/input supply" }, { "number": 46, "name": "VDD", "type": "Power", "function": "Core/PLL digital supply" }, { "number": 60, "name": "VDD", "type": "Power", "function": "Core/PLL digital supply" }, { "number": 26, "name": "VDDO0", "type": "Power", "function": "Output bank 0 supply" }, { "number": 29, "name": "VDDO1", "type": "Power", "function": "Output bank 1 supply" }, { "number": 33, "name": "VDDO2", "type": "Power", "function": "Output bank 2 supply" }, { "number": 36, "name": "VDDO3", "type": "Power", "function": "Output bank 3 supply" }, { "number": 12, "name": "INTRB", "type": "Output", "function": "Active‑LOW aggregated notify" }, { "number": 11, "name": "OEB", "type": "Input", "function": "Output enable (HIGH disables)" }, { "number": 6, "name": "RSTB", "type": "Input", "function": "Reset (active‑LOW); on‑chip pull‑up" }, { "number": 18, "name": "SDAIO", "type": "I/O", "function": "I²C SDA / SPI SDI" }, { "number": 16, "name": "SCLK", "type": "I/O", "function": "I²C SCL / SPI SCLK" }, { "number": 19, "name": "CSB/A0", "type": "Input", "function": "SPI CSB / I²C A0" }, { "number": 17, "name": "SDO/A1", "type": "I/O", "function": "SPI SDO / I²C A1" }, { "number": 39, "name": "I2C1_SPI0", "type": "Input", "function": "Serial interface select (1=I²C)" }, { "number": -1, "name": "ePad", "type": "GND", "function": "Exposed ground pad" } ], "absolute_maximum": { "supply_voltage_V": { "min": -0.5, "max": 3.63 }, "io_voltage_V": { "min": -0.5, "max": 3.63 }, "storage_temperature_C": { "min": -55, "max": 150 }, "junction_temperature_C_max": 125, "programming_voltage_V": { "min": 2.375, "typ": 2.5, "max": 2.625 }, "ESD_HBM_V": 2000, "ESD_CDM_V": 750, "latchup_mA": 100, "MSL": 3 }, "package": { "options": [ "64‑QFN, 9×9 mm" ], "notes": [ "Integrated MEMS resonator reference architecture (no external crystal required for on-chip reference); device also supports external XO inputs", "Use recommended AC/DC terminations per output standard; LVDS/LVDS‑Boost/LVPECL preferred for AC‑coupled", "RSTB / FLEXIO / I²C/SPI at 1.8 V: use series resistor (~4.7 kΩ) if driven from 2.5/3.3 V logic" ] }, "ordering_information": { "example": "SiT95317 A I - X Y Y Y Y Y - T", "fields": { "family": "SiT95317", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X/Y characters = pre‑programmed startup config ID", "packaging": { "T": "Tape \u0026 Reel" } } } }, { "product_name": "SiT95901", "product_type": "Ultra Low‑Power Dual I²C Real‑Time Clock (RTC), DFN‑12 3×3 mm", "overview": { "description": "Ultra‑low power RTC/calendar with dual 7‑bit I²C slave interfaces, built‑in 32.768 kHz time base (crystal or MEMS), auto VCC↔VBAT switchover, programmable alarm and square‑wave CLKOUT, and on‑chip battery‑backed SRAM.", "features": [ "Timekeeping with leap‑year compensation to year 2100; 24‑hour or 12‑hour (AM/PM)", "Daylight‑Saving mode (forward/back per rules in datasheet)", "One time‑of‑day alarm with ALRT# output; status/interrupt flags (AF/OF/RTC_F/CIF)", "Dual I²C buses (primary/secondary) up to 400 kHz; ownership control (TWO/MWO)", "Battery‑backed 128‑byte SRAM", "Programmable CLKOUT: 32.768 kHz / 1.024 kHz / 32 Hz / 1 Hz", "Auto power‑level detect and VCC→VBAT switchover; oscillator fail detection", "Low current RTC on VBAT: typ 0.6–0.7 µA (25 °C / across temp), max 1.0–1.5 µA", "ESD: 2 kV HBM, 1 kV CDM; industrial temperature −40 to +85 °C", "Package: DFN‑12, 3×3 mm" ], "applications": [ "Server and computer precision timekeeping", "I/O controller hub / BMC co‑management", "Unattended operation timers", "Consumer products", "Industrial control" ] }, "electrical_characteristics": { "supplies": { "VCC_V": { "min": 1.7, "max": 3.6 }, "VBAT_V": { "min": 1.55, "max": 3.6 }, "icc_active_mA_max": 1.0, "ibat_timekeeping_25C_µA": { "typ": 0.6, "max": 1.0 }, "ibat_timekeeping_temp_µA": { "typ": 0.7, "max": 1.5 }, "ibat_peak_mA_max": 1.0, "switchover_thresholds_V": { "Vsw_1_VCC_falling": { "min": 1.4, "typ": 1.45, "max": 1.5 }, "Vsw_2_VCC_rising": { "min": 1.55, "typ": 1.6, "max": 1.65 } } }, "io_levels": { "VI_input_range_V": { "min": -0.5, "max": 3.6 }, "VIL_max_V": "0.3×VCC", "VIH_min_V": "0.7×VCC", "ILI_µA": { "min": -1, "max": 1 }, "RTC_CLR_VIH_V": { "min": 1.2, "max": 3.6 }, "RTC_CLR_VIL_V": { "min": -0.3, "max": 0.5 }, "CIN_pF": 1, "VOH_V": { "min": "0.8×VCC", "max": "VCC" }, "VOL_V": { "min": 0, "max": "0.2×VCC" }, "IOH_CLKOUT_mA": { "min": 1, "typ": 3 }, "IOL_SDA_ALERT_mA": { "min": 3, "typ": 8.5 }, "IOL_CLKOUT_mA": { "min": 1, "typ": 4 } }, "io_logic": { "i2c_addresses": { "rtc_7bit": "0x6F", "sram_7bit": "0x57" }, "i2c_speeds_kHz": [ 100, 400 ], "i2c_timeouts_ms": { "min": 25, "max": 35 }, "i2c_timing": { "tBUF_µs_min": 1.3, "tSU_STA_µs_min": 0.6, "tHD_STA_µs_min": 0.6, "tSU_DAT_ns_min": 100, "tHD_DAT_µs_min": 0.0, "tR_ns_max": 300, "tF_ns_max": 300, "tHIGH_µs_min": 0.6, "tLOW_µs_min": 1.3, "tSU_STO_µs_min": 0.6, "CB_pF_max": 400, "TVD_DAT_µs_max": 0.9, "TSP_ns_max": 50 } }, "crystal": { "frequency_kHz": 32.768, "accuracy_ppm_nominal": { "min": -23, "max": 23 }, "accuracy_ppm_temp_window": { "temp_range": "0…+40 °C", "min": -46, "max": 46 }, "load_capacitance_pF": 12.5, "esr_kΩ_max": 50, "drive_level_nW_typ": 100 } }, "pins": [ { "number": 1, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 2, "name": "X1", "type": "Input", "function": "Crystal input" }, { "number": 3, "name": "X2", "type": "Output", "function": "Crystal output" }, { "number": 4, "name": "ALRT#", "type": "Output", "function": "Alert output (active‑LOW, open‑drain)" }, { "number": 5, "name": "CLKOUT", "type": "Output", "function": "Programmable clock output" }, { "number": 6, "name": "RTC_CLR#", "type": "Input", "function": "Active‑LOW clear internal memory (ext pull‑up)" }, { "number": 7, "name": "SCL2", "type": "Input", "function": "Secondary I²C SCL" }, { "number": 8, "name": "SDA2", "type": "I/O", "function": "Secondary I²C SDA" }, { "number": 9, "name": "SCL1", "type": "Input", "function": "Primary I²C SCL" }, { "number": 10, "name": "SDA1", "type": "I/O", "function": "Primary I²C SDA" }, { "number": 11, "name": "VBAT", "type": "Power", "function": "Backup battery supply" }, { "number": 12, "name": "VCC", "type": "Power", "function": "Main supply for logic, I²C, memory" }, { "number": -1, "name": "EPAD", "type": "Ground", "function": "Thermal pad to GND" } ], "absolute_maximum": { "VCC_V_max": 3.6, "ICC_mA_max": 1, "VBAT_V_max": 3.6, "IBAT_µA_max": 10, "VI_input_V_max": 3.6, "VO_output_V_max": 3.6, "IIN_mA_max": 10, "IOUT_mA_max": 10, "Ptot_mW_max": 3.6, "ESD_HBM_V_max": 2000, "ESD_CDM_V_max": 1000, "Latchup_mA_max": 200, "Storage_temperature_°C_max": 150 }, "package": { "options": [ "DFN‑12, 3×3 mm" ], "notes": [ "Recommended land pattern and tape‑and‑reel per datasheet", "Top marking shows part code, lot, and SiTime logo" ] }, "ordering_information": { "example": "SiT95901 A I - P", "fields": { "family": "SiT95901", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } } }, { "product_name": "SiT92206", "product_type": "6‑Output Differential + 1 LVCMOS Ultra‑Low‑Jitter Buffer (36‑QFN 6×6 mm)", "overview": { "description": "2.1 GHz 6‑output low‑jitter fan‑out buffer with 3:1 input selection (2 universal inputs + crystal), two 3‑output differential banks (A,B) plus one LVCMOS REFOUT; pin‑controlled output standards (LVPECL/LVDS/HCSL/Hi‑Z).", "features": [ "Additive jitter ≈55–60 fs RMS (10 kHz–20 MHz)", "Universal inputs accept LVPECL, LVDS, LVCMOS, CML (AC‑coupled), HCSL, SSTL; DC–2.1 GHz", "Crystal input 8–50 MHz; bypass/overdrive up to 250 MHz (≤1.8 Vpp on OSC pins)", "Two output banks independently set to LVPECL/LVDS/HCSL/Hi‑Z; REFOUT LVCMOS", "Typical output skew 30 ps; noise floor −159 dBc/Hz", "Core 3.3 V/2.5 V; outputs 3.3/2.5 V (HCSL 1.8 V supported); REFOUT 3.3/2.5/1.8 V", "High PSRR: about −67 dBc (PECL), −70 dBc (LVDS), −67.7 dBc (HCSL)", "PCIe Gen1–Gen6 compliant", "Package: 36‑QFN 6×6 mm" ], "applications": [ "Clock/data distribution", "PCIe common‑clock trees", "Level translation across I/O standards" ] }, "electrical_characteristics": { "absolute_maximum": { "VCC_V": { "min": -0.3, "max": 3.6 }, "VCCO_V": { "min": -0.3, "max": 3.6 }, "VIN_non_osc_V": { "min": -0.3, "max": 3.6 }, "OSCIN_V_max": 1.8, "storage_temperature_°C": { "min": -55, "max": 150 }, "MSL": 3 }, "recommended_operating": { "VCC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.45 }, { "min": 2.375, "typ": 2.5, "max": 2.625 } ], "VCCO_AB_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.45 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "VCCOC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.45 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "ambient_temperature_°C": { "min": -40, "max": 85 }, "junction_temperature_°C_max": 125 }, "current_consumption": { "ICC_core_mA": { "typ": 16.5, "max": 19.8 }, "ICC_core_XO_selected_mA_max": 14, "ICC_dyn_at_2100MHz_mA": { "typ": 25, "max": 33 }, "ICCO_bank_mA": { "LVPECL": { "typ": 109, "max": 130.8 }, "LVDS": { "typ": 40, "max": 49 }, "HCSL": { "typ": 76, "max": 91.2 } }, "ICCO_LVCMOS_200MHz_mA": { "VCCO_3V3": { "typ": 6, "max": 7.2 }, "VCCO_2V5": { "typ": 4.5, "max": 5.5 } } }, "psrr_dBc_typ": { "LVPECL": -67, "LVDS": -70, "HCSL": -67.7 }, "inputs": { "frequency_range_MHz": { "min": 0, "max": 2100 }, "single_ended_VIH_V_min": { "VCC_3V3": 2.0, "VCC_2V5": 1.6 }, "single_ended_VIL_V_max": { "VCC_3V3": 1.3, "VCC_2V5": 0.9 }, "single_ended_swing_Vpp": { "min": 0.3, "max": 2.0 }, "differential_swing_VID_V": { "min": 0.15, "max": 1.3 } }, "crystal": { "frequency_range_MHz": { "min": 8, "max": 50 }, "overdrive_external_clock_MHz_max": 250, "CL_pF": { "min": 6, "typ": 8, "max": 10 }, "ESR_Ω": { "typ": 35, "max": 60 }, "Co_pF": { "typ": 2, "max": 3 }, "drive_level_µW": { "typ": 100, "max": 200 }, "crystal_phase_jitter_fs_rms_typ": 155 }, "outputs": { "LVPECL": { "fmax_MHz": { "≥600mV": 1200, "≥400mV": 2100 }, "jitter_fs_rms_typ": 55, "duty_cycle_%": [ 45, 55 ], "VOD_mV": { "min": 475, "typ": 678, "max": 960 }, "tr_tf_ps_typ": 210, "tpd_ps": { "typ": 876, "max": 1100 } }, "LVDS": { "fmax_MHz": { "≥250mV": 1600, "≥200mV": 2100 }, "jitter_fs_rms_typ": 60, "duty_cycle_%": [ 45, 55 ], "VOD_mV": { "min": 247, "max": 454 }, "tpd_ps": { "typ": 840, "max": 1100 }, "skew_ps_typ": 30 }, "HCSL": { "fmax_MHz": 700, "jitter_fs_rms_typ": 55, "duty_cycle_%": [ 45, 55 ], "tpd_ps": { "typ": 825, "max": 1100 } }, "LVCMOS": { "fmax_MHz": 250, "jitter_fs_rms_typ": { "VCCO_3V3": 55, "VCCO_2V5": 63 }, "duty_cycle_%": { "≤200MHz": [ 45, 55 ], "\u003e200–250MHz": [ 40, 60 ] }, "tr_tf_ps": { "typ": 250, "max": 450 } } } }, "package": { "options": [ "36‑QFN 6×6 mm" ] }, "ordering_information": { "example": "SiT92206 A I − P", "fields": { "family": "SiT92206", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 2, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 3, "name": "CLKOUTA0", "type": "Output", "function": "Bank A0 P — differential output; type set by CLKOUTA_TYPE" }, { "number": 4, "name": "CLKOUTA0*", "type": "Output", "function": "Bank A0 N — differential output; type set by CLKOUTA_TYPE" }, { "number": 5, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 6, "name": "CLKOUTA1", "type": "Output", "function": "Bank A1 P — differential output; type set by CLKOUTA_TYPE" }, { "number": 7, "name": "CLKOUTA1*", "type": "Output", "function": "Bank A1 N — differential output; type set by CLKOUTA_TYPE" }, { "number": 8, "name": "CLKOUTA2", "type": "Output", "function": "Bank A2 P — differential output; type set by CLKOUTA_TYPE" }, { "number": 9, "name": "CLKOUTA2*", "type": "Output", "function": "Bank A2 N — differential output; type set by CLKOUTA_TYPE" }, { "number": 10, "name": "CLKOUTA_TYPE0", "type": "Control", "function": "Bank A output buffer type select (with TYPE1)" }, { "number": 11, "name": "VCC", "type": "Power", "function": "Core supply 3.3/2.5 V" }, { "number": 12, "name": "OSCIN", "type": "Input", "function": "Crystal input; can accept AC‑coupled single‑ended overdrive (≤1.8 Vpp)" }, { "number": 13, "name": "OSCOUT", "type": "Output", "function": "Crystal output; leave floating if OSCIN is driven by single‑ended clock" }, { "number": 14, "name": "CLKIN_SEL0", "type": "Control", "function": "Clock input select bit 0" }, { "number": 15, "name": "CLKIN0", "type": "Input", "function": "Universal clock input 0 (+) — differential/single‑ended" }, { "number": 16, "name": "CLKIN0*", "type": "Input", "function": "Universal clock input 0 (−) — differential/single‑ended" }, { "number": 17, "name": "CLKIN_SEL1", "type": "Control", "function": "Clock input select bit 1" }, { "number": 18, "name": "CLKOUTB_TYPE0", "type": "Control", "function": "Bank B output buffer type select (with TYPE1)" }, { "number": 19, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 20, "name": "CLKOUTB2*", "type": "Output", "function": "Bank B2 N — differential output; type set by CLKOUTB_TYPE" }, { "number": 21, "name": "CLKOUTB2", "type": "Output", "function": "Bank B2 P — differential output; type set by CLKOUTB_TYPE" }, { "number": 22, "name": "CLKOUTB1*", "type": "Output", "function": "Bank B1 N — differential output; type set by CLKOUTB_TYPE" }, { "number": 23, "name": "CLKOUTB1", "type": "Output", "function": "Bank B1 P — differential output; type set by CLKOUTB_TYPE" }, { "number": 24, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 25, "name": "CLKOUTB0*", "type": "Output", "function": "Bank B0 N — differential output; type set by CLKOUTB_TYPE" }, { "number": 26, "name": "CLKOUTB0", "type": "Output", "function": "Bank B0 P — differential output; type set by CLKOUTB_TYPE" }, { "number": 27, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 28, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 29, "name": "CLKOUTB_TYPE1", "type": "Control", "function": "Bank B output buffer type select (with TYPE0)" }, { "number": 30, "name": "CLKIN1*", "type": "Input", "function": "Universal clock input 1 (−) — differential/single‑ended" }, { "number": 31, "name": "CLKIN1", "type": "Input", "function": "Universal clock input 1 (+) — differential/single‑ended" }, { "number": 32, "name": "VCC", "type": "Power", "function": "Core supply 3.3/2.5 V" }, { "number": 33, "name": "REFOUT", "type": "Output", "function": "LVCMOS clock out synchronized to selected clock; enable via REFOUT_EN" }, { "number": 34, "name": "VCCOC", "type": "Power", "function": "REFOUT supply 3.3/2.5/1.8 V" }, { "number": 35, "name": "REFOUT_EN", "type": "Control", "function": "Enable LVCMOS REFOUT (glitch‑free enable/disable)" }, { "number": 36, "name": "CLKOUTA_TYPE1", "type": "Control", "function": "Bank A output buffer type select (with TYPE0)" }, { "number": 0, "name": "GND-EPAD", "type": "Ground", "function": "Exposed pad ground" } ] }, { "product_name": "SiT92113", "product_type": "5‑Output Ultra‑Low‑Jitter LVCMOS Fan‑Out Buffer (24‑QFN 4×4 mm)", "overview": { "description": "250 MHz 5‑output LVCMOS fan‑out buffer with 2:1 input selection (universal input or crystal), two VDDO output domains for level translation, pin‑controlled enable; very low additive jitter.", "features": [ "Additive jitter as low as 21 fs RMS (conditions dependent)", "Universal inputs accept LVPECL, LVDS, LVCMOS, HCSL, SSTL; up to 250 MHz", "Crystal input 8–50 MHz; XO bypass/overdrive up to 250 MHz (≤1.5 V on OSC pins)", "Independent VDDO domains for outputs (3.3/2.5/1.8/1.5 V)", "Typical output skew 30–40 ps", "Package: 24‑QFN 4×4 mm" ], "applications": [ "Carrier Ethernet", "5G/Small cells", "General clock distribution" ] }, "electrical_characteristics": { "absolute_maximum": { "VDD_V": { "min": -0.5, "max": 3.6 }, "VDDO_V": { "min": -0.5, "max": 3.6 }, "VIN_non_osc_V": { "min": -0.3, "max": "VDD+0.3" }, "OSCIN_V_max": 1.5, "storage_temperature_°C": { "min": -55, "max": 150 }, "junction_temperature_°C_max": 125, "MSL": 3 }, "recommended_operating": { "ambient_temperature_°C": { "min": -40, "max": 105 }, "VDD_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 } ], "VDDO_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.6, "typ": 1.8, "max": 2.0 }, { "min": 1.35, "typ": 1.5, "max": 1.65 } ] }, "inputs": { "frequency_range_MHz": { "max": 250 }, "differential_swing_VID_V": { "min": 0.15, "max": 1.3 }, "single_ended_VIH_V_min": { "VDD_3V3": 2.0, "VDD_2V5": 1.6 }, "single_ended_VIL_V_max": { "VDD_3V3": 1.3, "VDD_2V5": 0.9 }, "slew_rate_V_per_ns_min": 2 }, "crystal": { "frequency_range_MHz": { "min": 8, "max": 50 }, "overdrive_external_clock_MHz_max": 250, "CL_pF": { "min": 6, "typ": 8, "max": 10 }, "ESR_Ω": { "typ": 35, "max": 60 }, "Co_pF": { "typ": 2, "max": 3 }, "drive_level_µW": { "typ": 100, "max": 200 } }, "outputs": { "LVCMOS": { "fmax_MHz": 250, "duty_cycle_%": { "≤200MHz": [ 45, 55 ], "\u003e200–250MHz": [ 40, 60 ] }, "VOH_V_min": { "3.3V": 2.6, "2.5V": 1.8, "1.8V": 1.2, "1.5V": 0.95 }, "VOL_V_max": { "3.3/2.5V": 0.5, "1.8V": 0.4, "1.5V": 0.35 }, "Zout_Ω": [ 15, 28 ], "skew_ps_typ": 35, "rise_fall_ps_typ": 605, "additive_jitter_fs_rms_range": [ 21, 233 ] } } }, "package": { "options": [ "24‑QFN 4×4 mm" ] }, "ordering_information": { "example": "SiT92113 A I − P", "fields": { "family": "SiT92113", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": "DAP", "name": "DAP", "type": "Ground", "function": "Exposed pad ground" }, { "number": 1, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 2, "name": "VDDO", "type": "Power", "function": "Output supply for CLKOUT0–1 (3.3/2.5/1.8/1.5 V)" }, { "number": 3, "name": "CLKOUT0", "type": "Output", "function": "LVCMOS output 0" }, { "number": 4, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 5, "name": "CLKOUT1", "type": "Output", "function": "LVCMOS output 1" }, { "number": 6, "name": "VDDO", "type": "Power", "function": "Output supply for CLKOUT0–1 (3.3/2.5/1.8/1.5 V)" }, { "number": 7, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 8, "name": "VDD", "type": "Power", "function": "Core/input supply 3.3/2.5 V" }, { "number": 9, "name": "OSCIN", "type": "Input", "function": "Crystal input; XO bypass/overdrive ≤1.5 V" }, { "number": 10, "name": "OSCOUT", "type": "Output", "function": "Crystal output; float if OSCIN is overdriven" }, { "number": 11, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 12, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 13, "name": "CLKOUT2", "type": "Output", "function": "LVCMOS output 2" }, { "number": 14, "name": "VDDO", "type": "Power", "function": "Output supply for CLKOUT2–4 (3.3/2.5/1.8/1.5 V)" }, { "number": 15, "name": "CLKOUT3", "type": "Output", "function": "LVCMOS output 3" }, { "number": 16, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 17, "name": "CLKOUT4", "type": "Output", "function": "LVCMOS output 4" }, { "number": 18, "name": "VDDO", "type": "Power", "function": "Output supply for CLKOUT2–4 (3.3/2.5/1.8/1.5 V)" }, { "number": 19, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 20, "name": "CLKIN*", "type": "Input", "function": "Complementary universal input (−)" }, { "number": 21, "name": "CLKIN", "type": "Input", "function": "Universal input (+)" }, { "number": 22, "name": "SEL", "type": "Control", "function": "Input select (0: CLKIN; 1: Crystal/Bypass); internal pulldown" }, { "number": 23, "name": "VDD", "type": "Power", "function": "Core/input supply 3.3/2.5 V" }, { "number": 24, "name": "OE", "type": "Control", "function": "Outputs enable (1)/Hi‑Z (0); internal pulldown" } ] }, { "product_name": "SiT92114", "product_type": "1:4 High‑Performance LVCMOS Buffer (8‑DFN 2×2 mm / 8‑TSSOP 3.0×4.4 mm)", "overview": { "description": "200 MHz 1:4 LVCMOS buffer with \u003c50 fs additive jitter, 3.3 V‑tolerant input and synchronous glitch‑free output enable (1G).", "features": [ "Additive jitter \u003c50 fs RMS", "Pin‑to‑pin skew \u003c50 ps", "3.3 V‑tolerant CLKIN", "Integrated ~50 Ω output path for 50 Ω channels", "VDD 1.8–3.3 V; FMAX 200 MHz", "Packages: 8‑DFN 2.0×2.0 mm and 8‑TSSOP 3.0×4.4 mm" ], "applications": [ "5G/4G base stations", "Telecom equipment", "Servers" ] }, "electrical_characteristics": { "absolute_maximum": { "VDD_V": { "max": 3.6 }, "IO_V": { "min": -0.4, "max": "VDD+0.3" }, "CLKIN_V": { "min": -0.4, "max": 3.465 }, "ambient_temperature_°C": { "min": -40, "max": 105 }, "storage_temperature_°C": { "min": -65, "max": 150 }, "junction_temperature_°C_max": 150, "MSL": 3 }, "recommended_operating": { "VDD_V": { "min": 1.71, "max": 3.465 }, "ambient_temperature_°C": { "min": -40, "max": 105 } }, "inputs": { "CLKIN": { "type": "LVCMOS", "tolerance": "3.3 V tolerant", "slew_rate_V_per_ns_min": 2 } }, "outputs": { "LVCMOS": { "fmax_MHz": 200, "enable_disable_cycles": { "25MHz": 3, "200MHz": 5 }, "skew_ps": { "pin_to_pin": { "typ": 35, "max": 50 } }, "prop_delay_ns": { "min": 0.24, "max": 1.6 }, "rise_fall_ns": { "typ": 0.61, "max": 1.2 } } } }, "package": { "options": [ "8‑DFN 2.0×2.0 mm", "8‑TSSOP 3.0×4.4 mm" ] }, "ordering_information": { "example": "SiT92114 A I − P", "fields": { "family": "SiT92114", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +105 °C" }, "packaging": { "P": "4ku Tape \u0026 Reel", "TRDP": "TSSOP 4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "CLKIN", "type": "Input", "function": "Single‑ended LVCMOS clock input (3.3 V tolerant)" }, { "number": 2, "name": "1G", "type": "Control", "function": "Global output enable/disable; synchronous glitch‑free" }, { "number": 3, "name": "Y0", "type": "Output", "function": "LVCMOS output 0" }, { "number": 4, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 5, "name": "Y2", "type": "Output", "function": "LVCMOS output 2" }, { "number": 6, "name": "VDD", "type": "Power", "function": "Core supply 1.8–3.3 V" }, { "number": 7, "name": "Y3", "type": "Output", "function": "LVCMOS output 3" }, { "number": 8, "name": "Y1", "type": "Output", "function": "LVCMOS output 1" } ] }, { "product_name": "SiT92211", "product_type": "10‑Output Differential Ultra‑Low‑Jitter Buffer (48‑QFN 7×7 mm)", "overview": { "description": "2.1 GHz 10‑output low‑jitter fan‑out buffer with 3:1 input selection (2 universal inputs + crystal), two 5‑output differential banks (A,B) plus one LVCMOS REFOUT; pin‑controlled output standards (LVPECL/LVDS/HCSL/Hi‑Z).", "features": [ "Additive jitter ≈55 fs RMS (10 kHz–20 MHz)", "Universal inputs accept LVPECL, LVDS, LVCMOS, CML (AC‑coupled), HCSL, SSTL; DC–2.1 GHz", "Crystal input 8–50 MHz; bypass/overdrive up to 250 MHz (≤1.8 Vpp on OSC pins)", "Two output banks independently set to LVPECL/LVDS/HCSL/Hi‑Z; REFOUT LVCMOS", "Typical output skew 30 ps; noise floor −159 dBc/Hz", "Core 3.3 V/2.5 V; outputs 3.3/2.5 V (HCSL/REFOUT also 1.8 V)", "High PSRR: −67 dBc (PECL), −70 dBc (LVDS), −67.7 dBc (HCSL)", "PCIe Gen1–Gen6 compliant", "Package: 48‑QFN 7×7 mm" ], "applications": [ "Clock/data distribution", "PCIe common‑clock trees", "Level translation across I/O standards" ] }, "electrical_characteristics": { "absolute_maximum": { "VCC_V": { "min": -0.3, "max": 3.6 }, "VCCO_V": { "min": -0.3, "max": 3.6 }, "VIN_non_osc_V": { "min": -0.3, "max": 3.6 }, "OSCIN_V_max": 1.8, "storage_temperature_°C": { "min": -55, "max": 150 }, "MSL": 3 }, "recommended_operating": { "VCC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.45 }, { "min": 2.375, "typ": 2.5, "max": 2.625 } ], "VCCO_AB_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.45 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "VCCOC_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.45 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "ambient_temperature_°C": { "min": -40, "max": 85 }, "junction_temperature_°C_max": 125 }, "current_consumption": { "ICC_core_mA": { "typ": 16.5, "max": 19.8 }, "ICC_core_XO_selected_mA_max": 14, "ICC_dyn_at_2100MHz_mA": { "typ": 25, "max": 33 }, "ICCO_bank_mA": { "LVPECL": { "typ": 165, "max": 204 }, "LVDS": { "typ": 40, "max": 49 }, "HCSL": { "typ": 110, "max": 138 } }, "ICCO_LVCMOS_200MHz_mA": { "VCCO_3V3": { "typ": 6, "max": 7.2 }, "VCCO_2V5": { "typ": 4.5, "max": 5.5 } } }, "psrr_dBc_typ": { "LVPECL": -67, "LVDS": -70, "HCSL": -67.7 }, "inputs": { "frequency_range_MHz": { "min": 0, "max": 2100 }, "single_ended_VIH_V_min": { "VCC_3V3": 2.0, "VCC_2V5": 1.6 }, "single_ended_VIL_V_max": { "VCC_3V3": 1.3, "VCC_2V5": 0.9 }, "single_ended_swing_Vpp": { "min": 0.3, "max": 2.0 }, "differential_swing_VID_V": { "min": 0.15, "max": 1.3 } }, "crystal": { "frequency_range_MHz": { "min": 8, "max": 50 }, "overdrive_external_clock_MHz_max": 250, "CL_pF": { "min": 6, "typ": 8, "max": 10 }, "ESR_Ω": { "typ": 35, "max": 60 }, "Co_pF": { "typ": 2, "max": 3 }, "drive_level_µW": { "typ": 100, "max": 200 } }, "outputs": { "LVPECL": { "fmax_MHz": { "≥600mV": 1200, "≥400mV": 2100 }, "jitter_fs_rms_typ": 55, "duty_cycle_%": [ 45, 55 ], "VOD_mV": { "min": 475, "typ": 678, "max": 960 }, "tr_tf_ps_typ": 210, "tpd_ps": { "typ": 876, "max": 1100 } }, "LVDS": { "fmax_MHz": { "≥250mV": 1600, "≥200mV": 2100 }, "jitter_fs_rms_typ": 60, "duty_cycle_%": [ 45, 55 ], "VOD_mV": { "min": 247, "max": 454 }, "tpd_ps": { "typ": 840, "max": 1100 }, "skew_ps_typ": 30 }, "HCSL": { "fmax_MHz": 700, "jitter_fs_rms_typ": 55, "duty_cycle_%": [ 45, 55 ], "tpd_ps": { "typ": 825, "max": 1100 } }, "LVCMOS": { "fmax_MHz": 250, "jitter_fs_rms_typ": { "VCCO_3V3": 55, "VCCO_2V5": 63 }, "duty_cycle_%": { "≤200MHz": [ 45, 55 ], "\u003e200–250MHz": [ 40, 60 ] }, "tr_tf_ps": { "typ": 250, "max": 450 } } } }, "package": { "options": [ "48‑QFN 7×7 mm" ] }, "ordering_information": { "example": "SiT92211 A I − P", "fields": { "family": "SiT92211", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "CLKoutA0", "type": "Output", "function": "Bank A0 P — differential output; type set by CLKoutA_TYPE" }, { "number": 2, "name": "CLKoutA0*", "type": "Output", "function": "Bank A0 N — differential output; type set by CLKoutA_TYPE" }, { "number": 3, "name": "CLKoutA1", "type": "Output", "function": "Bank A1 P — differential output; type set by CLKoutA_TYPE" }, { "number": 4, "name": "CLKoutA1*", "type": "Output", "function": "Bank A1 N — differential output; type set by CLKoutA_TYPE" }, { "number": 6, "name": "CLKoutA2", "type": "Output", "function": "Bank A2 P — differential output; type set by CLKoutA_TYPE" }, { "number": 7, "name": "CLKoutA2*", "type": "Output", "function": "Bank A2 N — differential output; type set by CLKoutA_TYPE" }, { "number": 9, "name": "CLKoutA3", "type": "Output", "function": "Bank A3 P — differential output; type set by CLKoutA_TYPE" }, { "number": 10, "name": "CLKoutA3*", "type": "Output", "function": "Bank A3 N — differential output; type set by CLKoutA_TYPE" }, { "number": 11, "name": "CLKoutA4", "type": "Output", "function": "Bank A4 P — differential output; type set by CLKoutA_TYPE" }, { "number": 12, "name": "CLKoutA4*", "type": "Output", "function": "Bank A4 N — differential output; type set by CLKoutA_TYPE" }, { "number": 36, "name": "CLKoutB0", "type": "Output", "function": "Bank B0 P — differential output; type set by CLKoutB_TYPE" }, { "number": 35, "name": "CLKoutB0*", "type": "Output", "function": "Bank B0 N — differential output; type set by CLKoutB_TYPE" }, { "number": 34, "name": "CLKoutB1", "type": "Output", "function": "Bank B1 P — differential output; type set by CLKoutB_TYPE" }, { "number": 33, "name": "CLKoutB1*", "type": "Output", "function": "Bank B1 N — differential output; type set by CLKoutB_TYPE" }, { "number": 31, "name": "CLKoutB2", "type": "Output", "function": "Bank B2 P — differential output; type set by CLKoutB_TYPE" }, { "number": 30, "name": "CLKoutB2*", "type": "Output", "function": "Bank B2 N — differential output; type set by CLKoutB_TYPE" }, { "number": 28, "name": "CLKoutB3", "type": "Output", "function": "Bank B3 P — differential output; type set by CLKoutB_TYPE" }, { "number": 27, "name": "CLKoutB3*", "type": "Output", "function": "Bank B3 N — differential output; type set by CLKoutB_TYPE" }, { "number": 26, "name": "CLKoutB4", "type": "Output", "function": "Bank B4 P — differential output; type set by CLKoutB_TYPE" }, { "number": 25, "name": "CLKoutB4*", "type": "Output", "function": "Bank B4 N — differential output; type set by CLKoutB_TYPE" }, { "number": 44, "name": "REFOUT", "type": "Output", "function": "LVCMOS clock out synchronized to selected clock; enable via REFOUT_EN" }, { "number": 20, "name": "CLKin0", "type": "Input", "function": "Universal clock input 0 (+) — differential/single‑ended" }, { "number": 21, "name": "CLKin0*", "type": "Input", "function": "Universal clock input 0 (−) — differential/single‑ended" }, { "number": 41, "name": "CLKin1", "type": "Input", "function": "Universal clock input 1 (+) — differential/single‑ended" }, { "number": 40, "name": "CLKin1*", "type": "Input", "function": "Universal clock input 1 (−) — differential/single‑ended" }, { "number": 16, "name": "OSCIN", "type": "Input", "function": "Crystal input; can accept AC‑coupled single‑ended overdrive (≤1.8 Vpp)" }, { "number": 17, "name": "OSCOUT", "type": "Output", "function": "Crystal output; leave floating if OSCIN is driven by single‑ended clock" }, { "number": 15, "name": "VCC", "type": "Power", "function": "Core supply 3.3/2.5 V" }, { "number": 42, "name": "VCC", "type": "Power", "function": "Core supply 3.3/2.5 V" }, { "number": 5, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 8, "name": "VCCOA", "type": "Power", "function": "Bank A output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 32, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 29, "name": "VCCOB", "type": "Power", "function": "Bank B output supply 3.3/2.5 V (1.8 V for HCSL)" }, { "number": 45, "name": "VCCOC", "type": "Power", "function": "REFOUT supply 3.3/2.5/1.8 V" }, { "number": 0, "name": "GND-EPAD", "type": "Ground", "function": "Exposed pad ground" }, { "number": 13, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 18, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 24, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 37, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 48, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 43, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 14, "name": "CLKoutA_TYPE0", "type": "Control", "function": "Bank A output buffer type select (with TYPE1)" }, { "number": 47, "name": "CLKoutA_TYPE1", "type": "Control", "function": "Bank A output buffer type select (with TYPE0)" }, { "number": 23, "name": "CLKoutB_TYPE0", "type": "Control", "function": "Bank B output buffer type select (with TYPE1)" }, { "number": 39, "name": "CLKoutB_TYPE1", "type": "Control", "function": "Bank B output buffer type select (with TYPE0)" }, { "number": 46, "name": "REFOUT_EN", "type": "Control", "function": "Enable LVCMOS REFOUT (glitch‑free enable/disable)" }, { "number": 19, "name": "CLKin_SEL0", "type": "Control", "function": "Clock input select bit 0" }, { "number": 22, "name": "CLKin_SEL1", "type": "Control", "function": "Clock input select bit 1" }, { "number": 38, "name": "NC", "type": "NC", "function": "No connect; do not pull high (may be pulled low or left floating)" } ] }, { "product_name": "SiT92112", "product_type": "1:2 High‑Performance LVCMOS Buffer (8‑DFN 2.0×2.0 mm)", "overview": { "description": "Ultra‑low‑jitter 1:2 LVCMOS clock buffer with synchronous glitch‑free OE; operates from 1.8–3.3 V and accepts 3.3 V‑tolerant CLKIN.", "features": [ "Additive jitter \u003c50 fs RMS", "Very low pin‑to‑pin skew: \u003c50 ps", "Supply voltage: 1.8 V to 3.3 V", "3.3 V‑tolerant input clock (CLKIN)", "FMAX = 200 MHz", "Integrated serial termination for 50 Ω channel", "8‑pin, 2×2 mm DFN" ], "applications": [ "5G/4G base stations", "Telecom equipment", "Servers" ] }, "electrical_characteristics": { "absolute_maximum": { "VDD_V_max": 3.6, "IO_V": { "min": -0.4, "max": "VDD+0.3" }, "CLKIN_V": { "min": -0.4, "max": 3.465 }, "ambient_temperature_°C": { "min": -40, "max": 105 }, "storage_temperature_°C": { "min": -65, "max": 150 }, "junction_temperature_°C_max": 150, "soldering_temperature_°C_max": 260, "MSL": 3 }, "recommended_operating": { "VDD_V": { "min": 1.71, "max": 3.465 }, "ambient_temperature_°C": { "min": -40, "max": 105 } }, "dc_characteristics": { "1.8V": { "VIH_CLKIN_min": "0.7×VDD", "VIL_CLKIN_max": "0.3×VDD", "VIH_1G_min_V": 1.6, "VIL_1G_max_V": 0.6, "VOH_min_V": 1.4, "VOL_max_V": 0.4, "ZO_Ω_typ": 50, "CIN_pF_typ": 5, "IDD_mA": { "0.001MHz": [ 0.7, 1.7 ], "0.008MHz": [ 0.7, 1.7 ], "40MHz": [ 7.0, 8.3 ], "100MHz": [ 15.4, 18.5 ], "156.25MHz": [ 23.2, 29.5 ], "200MHz": [ 25.2, 36.8 ] } }, "2.5V": { "VIH_CLKIN_min": "0.7×VDD", "VIL_CLKIN_max": "0.3×VDD", "VIH_1G_min_V": 1.8, "VIL_1G_max_V": 0.7, "VOH_min_V": 1.9, "VOL_max_V": 0.5, "ZO_Ω_typ": 50, "CIN_pF_typ": 5, "IDD_mA": { "0.001MHz": [ 0.9, 2.0 ], "0.008MHz": [ 0.9, 2.0 ], "40MHz": [ 9.7, 11.2 ], "100MHz": [ 22.0, 26.5 ], "156.25MHz": [ 33.2, 42.7 ], "200MHz": [ 36.7, 52.4 ] } }, "3.3V": { "VIH_CLKIN_min": "0.7×VDD", "VIL_CLKIN_max": "0.3×VDD", "VIH_1G_min_V": 2.1, "VIL_1G_max_V": 0.8, "VOH_min_V": 2.4, "VOL_max_V": 0.7, "ZO_Ω_typ": 50, "CIN_pF_typ": 5, "IDD_mA": { "0.001MHz": [ 1.2, 2.2 ], "0.008MHz": [ 1.2, 2.2 ], "40MHz": [ 12.6, 15.5 ], "100MHz": [ 29.4, 35.3 ], "156.25MHz": [ 44.1, 57.2 ], "200MHz": [ 50.9, 72.7 ] } } }, "ac_characteristics": { "1.8V": { "input_freq_MHz": [ 0, 200 ], "input_freq_ac_coupled_MHz": [ 0.1, 200 ], "slew_rate_V_per_ns_min": 2, "input_swing_ac_V_min": 0.5, "rise_fall_ns_typ_max": [ 0.65, 0.9 ], "startup_time_ms_max": 3, "prop_delay_ns_min_max": [ 0.24, 1.6 ], "additive_jitter_ps_rms_max": 0.06, "output_skew_ps_typ_max": [ 35, 50 ], "enable_disable_cycles": { "25MHz": 3, "200MHz": 5 }, "duty_cycle_%": 50 }, "2.5V": { "input_freq_MHz": [ 0, 200 ], "input_freq_ac_coupled_MHz": [ 0.1, 200 ], "slew_rate_V_per_ns_min": 2, "input_swing_ac_V_min": 0.5, "rise_fall_ns_typ_max": [ 0.63, 1.2 ], "startup_time_ms_max": 3, "prop_delay_ns_min_max": [ 0.24, 1.6 ], "additive_jitter_ps_rms_max": 0.06, "output_skew_ps_typ_max": [ 35, 50 ], "enable_disable_cycles": { "25MHz": 3, "200MHz": 5 }, "duty_cycle_%": 50 }, "3.3V": { "input_freq_MHz": [ 0, 200 ], "input_freq_ac_coupled_MHz": [ 0.1, 200 ], "slew_rate_V_per_ns_min": 2, "input_swing_ac_V_min": 0.5, "rise_fall_ns_typ_max": [ 0.61, 0.9 ], "startup_time_ms_max": 3, "prop_delay_ns_min_max": [ 0.24, 1.6 ], "additive_jitter_ps_rms_max": 0.05, "output_skew_ps_typ_max": [ 35, 50 ], "enable_disable_cycles": { "25MHz": 3, "200MHz": 5 }, "duty_cycle_%": 50 } }, "esd": { "HBM_V": 2000, "CDM_V": 500 }, "thermal": { "theta_JA_°C_per_W": 75 } }, "package": { "options": [ "8‑DFN 2.0×2.0 mm" ] }, "ordering_information": { "example": "SiT92112 A I − P", "fields": { "family": "SiT92112", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +105 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "CLKIN", "type": "Input", "function": "Single‑ended clock input (3.3 V tolerant)" }, { "number": 2, "name": "1G", "type": "Control", "function": "Global output enable (HIGH=Enable); synchronous glitch‑free" }, { "number": 3, "name": "Y0", "type": "Output", "function": "LVCMOS output 0" }, { "number": 4, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 5, "name": "NC", "type": "NC", "function": "No connect" }, { "number": 6, "name": "VDD", "type": "Power", "function": "Core supply 1.8–3.3 V" }, { "number": 7, "name": "NC", "type": "NC", "function": "No connect" }, { "number": 8, "name": "Y1", "type": "Output", "function": "LVCMOS output 1" } ] }, { "product_name": "SiT92110", "product_type": "10‑Output LVCMOS Ultra‑Low‑Jitter Buffer (32‑QFN 5×5 mm)", "overview": { "description": "10‑output LVCMOS fan‑out buffer with 3:1 input selection (two universal + crystal), dual VDDO domains for level translation, synchronous glitch‑free OE; operates with core 1.8/2.5/3.3 V and outputs 1.5/1.8/2.5/3.3 V.", "features": [ "Additive jitter ≈50 fs RMS", "Typical output‑to‑output skew 30–40 ps", "Level translation via independent VDD (1.8/2.5/3.3 V) and VDDO (1.5/1.8/2.5/3.3 V)", "Universal inputs accept LVPECL, LVDS, LVCMOS, SSTL; crystal 8–50 MHz; XO bypass up to 250 MHz", "Glitch‑free OE synchronized to input clock", "Package: 32‑pin QFN 5×5 mm" ], "applications": [ "Clock/data distribution", "Level translation across I/O standards" ] }, "electrical_characteristics": { "absolute_maximum": { "VDD_V": { "min": -0.5, "max": 3.6 }, "VDDO_V": { "min": -0.5, "max": 3.6 }, "VIN_non_XTAL_V": { "min": -0.3, "max": "VDD+0.3" }, "XTAL_IN_V": { "min": -0.5, "max": 1.8 }, "storage_temperature_°C": { "min": -55, "max": 150 }, "junction_temperature_°C_max": 125, "MSL": 3 }, "recommended_operating": { "VDD_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.71, "typ": 1.8, "max": 1.89 } ], "VDDO_options_V": [ { "min": 3.135, "typ": 3.3, "max": 3.465 }, { "min": 2.375, "typ": 2.5, "max": 2.625 }, { "min": 1.6, "typ": 1.8, "max": 2.0 }, { "min": 1.35, "typ": 1.5, "max": 1.65 } ], "ambient_temperature_°C": { "min": -40, "max": 85 } }, "inputs": { "universal": { "diff_swing_Vpp": [ 0.15, 1.3 ], "common_mode_V": [ 0.25, "VDD−0.85" ], "VIH_single_ended_min_V": { "VDD_3V3": 2.0, "VDD_2V5": 1.6 }, "VIL_single_ended_max_V": { "VDD_3V3": 1.3, "VDD_2V5": 0.9 }, "slew_rate_V_per_ns_min": 2, "input_capacitance_fF_typ": 700, "input_freq_MHz_max": 250 }, "crystal": { "freq_range_MHz": [ 8, 50 ], "overdrive_bypass_MHz_max": 250, "CL_pF": [ 6, 8, 10 ], "ESR_Ω": [ 35, 60 ], "Co_pF": [ 2, 3 ], "drive_level_µW": [ 100, 200 ], "crystal_phase_jitter_fs_rms_typ": 155, "XTAL_IN_limits": { "Vpp_se": [ 1.0, 1.8 ], "slew_rate_V_per_ns_min": 0.2 } }, "select": { "SEL[1:0]": { "00": "CLK0", "01": "CLK1", "10": "Crystal / AC bypass", "11": "Crystal / DC bypass" } } }, "outputs": { "LVCMOS": { "fmax_MHz": { "universal_input": 250, "XTAL": 50 }, "duty_cycle_%": { "≤200MHz": [ 45, 55 ], "\u003e200–250MHz": [ 40, 60 ] }, "VOH_min_V": { "3.3V": 2.6, "2.5V": 1.8, "1.8V": 1.2, "1.5V": 0.95 }, "VOL_max_V": { "3.3/2.5V": 0.5, "1.8V": 0.4, "1.5V": 0.35 }, "Zout_Ω_typ": { "3.3V": 15, "2.5V": 18, "1.62V": 23, "1.35V": 28 }, "skew_ps_typ": { "3.465V": 40, "2.5V": 35, "1.62V": 31, "1.35V": 36 }, "enable_disable_cycles_max": 4, "t_input_to_output_ns_typ": { "3.465V": 1.4, "2.5V": 1.5, "1.62V": 2.0, "1.35V": 2.5 }, "additive_jitter_fs_rms_typ": { "3.465V": 21, "2.5V": 37, "1.62V": 87, "1.35V": 233 }, "rise_fall_ps_max": 605 } }, "power": { "core_static_mA_typ_max": [ 16, 19.8 ], "odr_static_mA_typ_max": [ 3.5, 4.2 ], "core_xtal_enabled_mA_typ_max": [ 11.5, 14 ] }, "thermal": { "theta_JA_°C_per_W": { "0m_s": 43.4, "1m_s": 38.7, "2m_s": 37.4 }, "theta_JB_°C_per_W": 16.62, "theta_JC_°C_per_W": 23.7, "psi_JT_°C_per_W": 0.75 } }, "package": { "options": [ "32‑QFN 5×5 mm" ] }, "ordering_information": { "example": "SiT92110 A I − P", "fields": { "family": "SiT92110", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "Q0", "type": "Output", "function": "LVCMOS output 0" }, { "number": 3, "name": "Q1", "type": "Output", "function": "LVCMOS output 1" }, { "number": 5, "name": "Q2", "type": "Output", "function": "LVCMOS output 2" }, { "number": 7, "name": "Q3", "type": "Output", "function": "LVCMOS output 3" }, { "number": 8, "name": "Q4", "type": "Output", "function": "LVCMOS output 4" }, { "number": 17, "name": "Q5", "type": "Output", "function": "LVCMOS output 5" }, { "number": 18, "name": "Q6", "type": "Output", "function": "LVCMOS output 6" }, { "number": 20, "name": "Q7", "type": "Output", "function": "LVCMOS output 7" }, { "number": 22, "name": "Q8", "type": "Output", "function": "LVCMOS output 8" }, { "number": 24, "name": "Q9", "type": "Output", "function": "LVCMOS output 9" }, { "number": 2, "name": "VDDO", "type": "Power", "function": "Output supply domain for Q0–Q4 (1.5/1.8/2.5/3.3 V)" }, { "number": 6, "name": "VDDO", "type": "Power", "function": "Output supply domain for Q0–Q4 (1.5/1.8/2.5/3.3 V)" }, { "number": 19, "name": "VDDO", "type": "Power", "function": "Output supply domain for Q5–Q9 (1.5/1.8/2.5/3.3 V)" }, { "number": 23, "name": "VDDO", "type": "Power", "function": "Output supply domain for Q5–Q9 (1.5/1.8/2.5/3.3 V)" }, { "number": 9, "name": "GNDO", "type": "Ground", "function": "Ground" }, { "number": 15, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 16, "name": "GNDO", "type": "Ground", "function": "Ground" }, { "number": 4, "name": "GNDO", "type": "Ground", "function": "Ground" }, { "number": 21, "name": "GNDO", "type": "Ground", "function": "Ground" }, { "number": 26, "name": "GND", "type": "Ground", "function": "Ground" }, { "number": 25, "name": "GNDO", "type": "Ground", "function": "Ground" }, { "number": 32, "name": "GNDO", "type": "Ground", "function": "Ground" }, { "number": 10, "name": "VDD", "type": "Power", "function": "Core supply 1.8/2.5/3.3 V" }, { "number": 11, "name": "XTAL_IN", "type": "Input", "function": "Crystal input; can be overdriven (≤1.8 Vpp)" }, { "number": 12, "name": "XTAL_OUT", "type": "Output", "function": "Crystal oscillator pin" }, { "number": 13, "name": "CLK0", "type": "Input", "function": "Primary universal input (non‑inverting)" }, { "number": 14, "name": "nCLK0", "type": "Input", "function": "Primary universal input (inverting)" }, { "number": 27, "name": "nCLK1", "type": "Input", "function": "Secondary universal input (inverting)" }, { "number": 28, "name": "CLK1", "type": "Input", "function": "Secondary universal input (non‑inverting)" }, { "number": 29, "name": "SEL1", "type": "Control", "function": "Input select (MSB)" }, { "number": 30, "name": "SEL0", "type": "Control", "function": "Input select (LSB)" }, { "number": 31, "name": "OE", "type": "Control", "function": "Outputs enable (1)/Hi‑Z (0); glitch‑free" } ] }, { "product_name": "SiT92318", "product_type": "8‑Output HCSL‑LP Differential Fan‑Out Buffer (DB800Z equivalent, 48‑VQFN 6×6 mm)", "overview": { "description": "8‑output HCSL‑LP differential fan‑out buffer with integrated 85 Ω terminations, designed to meet or exceed Intel DB800Z. Supports PCIe Gen1–Gen6/QPI/UPI, SMBus control, per‑pair OEb pins, and power‑good sequencing.", "features": [ "HCSL‑LP outputs with ZDIFF ≈ 85 Ω (no external terminations)", "Spread‑spectrum compatible; tracks spreading input clock", "Additive phase jitter (100 MHz): ~50 fs typ in 10 k–20 M band; ~12 fs RMS after PCIe Gen5 (CC) filter; ~8 fs RMS after PCIe Gen6 filter; ~10 fs RMS after DB800Z filter", "Programmable output slew control", "3.3 V VDDIN/VDD/VDDO supplies", "Hardware low‑power mode (CKPWRGD_PDN) and SMBus interface", "Typical 62 mA device current with 8 outputs enabled @100 MHz, 10 line + 2 pF each" ], "applications": [ "Servers (micro/tower/rack)", "Storage (SAN/HBA/NAS)", "Hardware accelerators" ] }, "electrical_characteristics": { "absolute_maximum": { "VDDIN_V_max": 3.63, "VDD_V_max": 3.63, "VDDO_V_max": 3.63, "VIL_min_V": "GND−0.5", "VIH_max_V": "VDD+0.5", "VIHSMB_max_V": 3.6, "storage_temperature_°C": { "min": -65, "max": 150 }, "junction_temperature_°C_max": 125, "ESD_HBM_V": 2000, "ESD_CDM_V": 500, "latchup_mA": 100, "MSL": 3 }, "recommended_operating": { "VDDIN_V": { "min": 2.97, "typ": 3.3, "max": 3.465 }, "VDD_V": { "min": 2.97, "typ": 3.3, "max": 3.465 }, "VDDO_V": { "min": 2.97, "typ": 3.3, "max": 3.465 }, "ambient_temperature_°C": { "min": -40, "max": 85 }, "junction_temperature_°C_max": 125 }, "power": { "IDD_VDDIN_mA_typ": 6.6, "IDD_VDD_mA_typ": 8.0, "IDD_VDDO_mA_typ_at100MHz_all_outputs": 48.0, "powerdown_currents_mA": { "VDDIN": 1.0, "VDD": 4.5, "VDDO": 5.3 }, "low_power_mode_currents_mA": { "VDDIN": 0.1, "VDD": 3.0, "VDDO": 0.1 } }, "inputs": { "CLKIN": { "frequency_Hz": { "min": 1, "max": 400000000 }, "diff_swing_V_min": 0.1, "slew_rate_V_per_ns": { "min": 0.2, "max": 4.0 }, "leakage_uA": { "min": -5, "max": 5 }, "duty_cycle_%": 50, "crossover_V": { "min": 0.1, "max": 0.9 } } }, "smbus": { "VIL_max_V": 0.8, "VIH_min_V": 2.1, "VDD_SMB_V": { "min": 2.7, "max": 3.6 }, "sink_current_mA": 4 }, "outputs": { "HCSL_LP_100MHz": { "slew_rate_V_per_ns": { "min": 2, "max": 4 }, "slew_match_%_max": 20, "Vhigh_mV_typ": 750, "Vlow_mV_typ": 0, "Vmax_mV": null, "Vmin_mV": null, "Vswing_mV": null, "Vcross_abs_mV_typ": 375, "Zdiff_ohm": { "typ": 85, "min": "85−5%", "max": "85+5%" }, "Zdiff_cross_ohm": { "typ": 85, "min": "85−20%", "max": "85+20%" }, "stabilization_time_ms": { "typ": 1.0, "max": 1.8 }, "OEb_latency_clocks": { "min": 2, "max": 3 }, "tdrive_PDb_us": { "typ": 76, "max": 300 }, "VOH_mV": { "min": 225, "max": 270 }, "VOL_mV": { "min": 10, "max": 120 }, "overshoot_mV": "+75 over VOH", "undershoot_mV": "−75 under VOL" } }, "timing": { "input_to_output_skew_ns_typ": 0.75, "output_to_output_skew_ps_max": 50 }, "pcie_phase_jitter": { "Gen1_CC": { "typ_ps_pp": 0.1 }, "Gen2_CC": { "typ_ps_rms": 0.08 }, "Gen3_CC": { "typ_ps_rms": 0.023 }, "Gen4_CC": { "typ_ps_rms": 0.023 }, "Gen5_CC": { "typ_ps_rms": 0.009 }, "Gen6_CC": { "typ_ps_rms": 0.006 } } }, "package": { "options": [ "48‑VQFN 6×6 mm" ], "epad": "GND" }, "ordering_information": { "example": "SiT92318 A I − XYYYYY − P", "fields": { "family": "SiT92318", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X= A/B for customer device; Y = 0..9, A..Z serial ID", "packaging": { "P": "4ku Tape \u0026 Reel" } } }, "pins": [ { "number": 1, "name": "CKPWRGD_PDN", "type": "Input", "function": "Power good / power‑down control (assert high to start; low enters PD)" }, { "number": 2, "name": "GNDIN", "type": "Ground", "function": "CLKIN receiver ground" }, { "number": 3, "name": "VDDIN", "type": "Power", "function": "3.3 V differential input receiver supply (treat as analog)" }, { "number": 4, "name": "CLKINP", "type": "Input", "function": "0.75 V differential true input" }, { "number": 5, "name": "CLKINN", "type": "Input", "function": "0.75 V differential complement input" }, { "number": 6, "name": "SMBDAT", "type": "I/O", "function": "SMBus data (3.3 V tolerant)" }, { "number": 7, "name": "SMBCLK", "type": "Input", "function": "SMBus clock (3.3 V tolerant)" }, { "number": 8, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 9, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 10, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 11, "name": "OEb0", "type": "Input", "function": "Active‑low enable for CLKOUT0 pair (PD)" }, { "number": 12, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 13, "name": "CLKOUT0P", "type": "Output", "function": "Differential true output (pair 0)" }, { "number": 14, "name": "CLKOUT0N", "type": "Output", "function": "Differential complement output (pair 0)" }, { "number": 15, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 16, "name": "CLKOUT1P", "type": "Output", "function": "Differential true output (pair 1)" }, { "number": 17, "name": "CLKOUT1N", "type": "Output", "function": "Differential complement output (pair 1)" }, { "number": 18, "name": "OEb1", "type": "Input", "function": "Active‑low enable for CLKOUT1 pair (PD)" }, { "number": 19, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 20, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 21, "name": "CLKOUT2P", "type": "Output", "function": "Differential true output (pair 2)" }, { "number": 22, "name": "CLKOUT2N", "type": "Output", "function": "Differential complement output (pair 2)" }, { "number": 23, "name": "OEb2", "type": "Input", "function": "Active‑low enable for CLKOUT2 pair (PD)" }, { "number": 24, "name": "OEb3", "type": "Input", "function": "Active‑low enable for CLKOUT3 pair (PD)" }, { "number": 25, "name": "CLKOUT3P", "type": "Output", "function": "Differential true output (pair 3)" }, { "number": 26, "name": "CLKOUT3N", "type": "Output", "function": "Differential complement output (pair 3)" }, { "number": 27, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 28, "name": "CLKOUT4P", "type": "Output", "function": "Differential true output (pair 4)" }, { "number": 29, "name": "CLKOUT4N", "type": "Output", "function": "Differential complement output (pair 4)" }, { "number": 30, "name": "OEb4", "type": "Input", "function": "Active‑low enable for CLKOUT4 pair (PD)" }, { "number": 31, "name": "OEb5", "type": "Input", "function": "Active‑low enable for CLKOUT5 pair (PD)" }, { "number": 32, "name": "CLKOUT5P", "type": "Output", "function": "Differential true output (pair 5)" }, { "number": 33, "name": "CLKOUT5N", "type": "Output", "function": "Differential complement output (pair 5)" }, { "number": 34, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 35, "name": "CLKOUT6P", "type": "Output", "function": "Differential true output (pair 6)" }, { "number": 36, "name": "CLKOUT6N", "type": "Output", "function": "Differential complement output (pair 6)" }, { "number": 37, "name": "OEb6", "type": "Input", "function": "Active‑low enable for CLKOUT6 pair (PD)" }, { "number": 38, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 39, "name": "CLKOUT7P", "type": "Output", "function": "Differential true output (pair 7)" }, { "number": 40, "name": "CLKOUT7N", "type": "Output", "function": "Differential complement output (pair 7)" }, { "number": 41, "name": "OEb7", "type": "Input", "function": "Active‑low enable for CLKOUT7 pair (PD)" }, { "number": 42, "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": 43, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 44, "name": "VDD", "type": "Power", "function": "3.3 V core supply" }, { "number": 45, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 46, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 47, "name": "NC", "type": "NC", "function": "No connect (recommend GND)" }, { "number": 48, "name": "NC/Hi/M/Lo", "type": "NC", "function": "User‑don’t‑care; any static level acceptable" }, { "number": 0, "name": "EPAD", "type": "Ground", "function": "Exposed pad ground" } ] }, { "product_name": "SiT92315", "product_type": "20‑Output HCSL‑LP Differential Fan‑Out Buffer (DB2000QL equivalent, 80‑LGA 6×6 mm)", "overview": { "description": "20‑output HCSL‑LP differential fan‑out buffer meeting Intel DB2000QL specs. Supports PCIe Gen1–Gen6/QPI/UPI. Control via SMBus, per‑pair OEb pins, or 3‑wire Side‑Band Interface (SBI).", "features": [ "HCSL‑LP outputs with ZDIFF ≈ 85 Ω; no external terminations", "Spread‑spectrum compatible; tracks spreading input clock", "Additive phase jitter (100 MHz): ~50 fs typ (10 k–20 M); ~12 fs RMS after PCIe Gen5 (CC); ~8 fs RMS after PCIe Gen6; ~10 fs RMS after DB2000QL filter", "Programmable output slew control; output‑to‑output skew \u003c50 ps", "3.3 V supplies (VDDIN/VDD/VDDO)", "Hardware low‑power mode (CKPWRGD_PDN)", "Typical 175 mA device current with 20 outputs enabled @100 MHz, 10 line + 2 pF each" ], "applications": [ "Servers (micro/tower/rack)", "Storage (SAN/HBA/NAS/SSDs)" ] }, "electrical_characteristics": { "absolute_maximum": { "VDDIN_V_max": 3.63, "VDD_V_max": 3.63, "VDDO_V_max": 3.63, "VIL_min_V": "GND−0.5", "VIH_max_V": "VDD+0.5", "VIHSMB_max_V": 3.6, "storage_temperature_°C": { "min": -65, "max": 150 }, "junction_temperature_°C_max": 125, "ESD_HBM_V": 2000, "ESD_CDM_V": 500, "latchup_mA": 100, "MSL": 3 }, "recommended_operating": { "VDDIN_V": { "min": 2.97, "typ": 3.3, "max": 3.465 }, "VDD_V": { "min": 2.97, "typ": 3.3, "max": 3.465 }, "VDDO_V": { "min": 2.97, "typ": 3.3, "max": 3.465 }, "ambient_temperature_°C": { "min": -40, "max": 85 }, "junction_temperature_°C_max": 125 }, "power": { "IDD_VDDIN_mA_typ_max": [ 7.0, 8.6 ], "IDD_VDD_mA_typ_max": [ 20.0, 36.0 ], "IDD_VDDO_mA_per_output_typ_max": [ 7.7, 9.0 ], "powerdown_currents": { "VDDIN_uA": { "typ": 1, "max": 20 }, "VDD_mA": { "typ": 3.3, "max": 4 }, "VDDO_mA": { "typ": 1.2, "max": 1.4 } } }, "inputs": { "CLKIN": { "frequency_Hz": { "min": 1, "max": 400000000 }, "diff_swing_V_min": 0.1, "slew_rate_V_per_ns": { "min": 0.2, "max": 4.0 }, "leakage_uA": { "min": -5, "max": 5 }, "duty_cycle_%": 50, "crossover_V": { "min": 0.1, "max": 0.9 } } }, "smbus": { "VIL_max_V": "0.3×VDD", "VIH_min_V": "0.7×VDD", "VOH_min_V": "0.75×VDD (IOH=−2 mA)", "VOL_max_V": "0.25×VDD (IOL=2 mA)", "rise_time_ns_max": 1000, "fall_time_ns_max": 300, "frequency_kHz": { "min": 4, "max": 400 } }, "outputs": { "HCSL_LP_100MHz": { "slew_rate_V_per_ns": { "min": 2, "max": 4 }, "slew_match_%_max": 20, "Vhigh_mV": { "min": 650, "typ": 800, "max": 950 }, "Vlow_mV": { "min": 0, "max": 20 }, "Vmax_mV": { "typ": 870, "min": null, "max": 1055 }, "Vmin_mV": { "min": -125, "typ": -33, "max": 29 }, "Vcross_abs_mV": { "min": 365, "typ": 457, "max": 541 }, "Vcross_var_mV": { "typ": 19, "max": 28 }, "stabilization_time_ms": { "typ": 1.0, "max": 1.8 }, "OEb_latency_clocks": { "min": 2, "max": 3 }, "tdrive_PDb_us": { "typ": 76, "max": 300 }, "Zdiff_ohm": { "min": 80, "typ": 85, "max": 90 } } }, "timing": { "input_to_output_skew_ns": { "min": 0.55, "typ": 0.73, "max": 0.91 }, "tpd_drift_ps_per_°C": { "typ": 1.0, "max": 1.65 }, "output_to_output_skew_ps": { "typ": 25, "max": 50 }, "duty_cycle_distortion_%": { "min": -0.7, "typ": 0.1, "max": 0.7 } }, "pcie_phase_jitter": { "Gen1_CC": { "typ_ps_pp": 1.0, "max_ps_pp": 2.0 }, "Gen2_CC": { "typ_ps_rms": 0.08, "max_ps_rms": 0.133 }, "Gen3_CC": { "typ_ps_rms": 0.032, "max_ps_rms": 0.049 }, "Gen4_CC": { "typ_ps_rms": 0.032, "max_ps_rms": 0.049 }, "Gen5_CC": { "typ_ps_rms": 0.013, "max_ps_rms": 0.019 }, "Gen6_CC": { "typ_ps_rms": 0.009, "max_ps_rms": 0.012 } }, "thermal": { "theta_JA_°C_per_W": { "0m_s": 40.84, "1m_s": 36.2, "2m_s": 35.3 }, "theta_JB_°C_per_W": 37.2, "theta_JC_°C_per_W": 30.5, "psi_JT_°C_per_W": 21.26 } }, "package": { "options": [ "80‑LGA 6×6 mm" ], "epad": "GND" }, "ordering_information": { "example": "SiT92315 A I − XYYYYY − P", "fields": { "family": "SiT92315", "revision": { "A": "silicon revision" }, "temp_range": { "I": "−40 to +85 °C" }, "customer_code": "X= A/B for customer device; Y = 0..9, A..Z serial ID", "packaging": { "N": "500u Tape \u0026 Reel", "P": "4ku Tape \u0026 Reel" } } }, "control_interfaces": { "OE_pins": "Per‑pair active‑low OExb pins", "SMBus": { "address_selection": "Tri‑level SADR1_tri/SADR0_tri", "bytes_read_count": "configurable" }, "SBI": { "pins": [ "DATA (OEb5)", "CLK (OEb6)", "SHFT_LDN (OEb10)" ], "max_clk_MHz": 25, "mask_registers": true } }, "pins": [ { "number": "B2", "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": "B11", "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": "L2", "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": "L11", "name": "VDDO", "type": "Power", "function": "Output driver supply 3.3 V" }, { "number": "B6", "name": "VDD", "type": "Power", "function": "3.3 V core (analog) supply" }, { "number": "H2", "name": "VDDIN", "type": "Power", "function": "3.3 V differential input receiver supply (analog)" }, { "number": "B4", "name": "SADR0_tri", "type": "Input", "function": "SMBus address strap, tri‑level (PU/PD to VDD/2)" }, { "number": "B8", "name": "SADR1_tri", "type": "Input", "function": "SMBus address strap, tri‑level (PU/PD to VDD/2)" }, { "number": "E2", "name": "SB_EN", "type": "Input", "function": "Side‑Band enable (1: SBI active; 0: traditional OE/SMBus)" }, { "number": "L4", "name": "SMBDAT", "type": "I/O", "function": "SMBus data (3.3 V tolerant)" }, { "number": "L5", "name": "SMBCLK", "type": "I/O", "function": "SMBus clock (3.3 V tolerant)" }, { "number": "G1", "name": "CLKINP", "type": "Input", "function": "0.75 V differential true input" }, { "number": "H1", "name": "CLKINN", "type": "Input", "function": "0.75 V differential complement input" }, { "number": "J1", "name": "CLKOUT0P", "type": "Output", "function": "Differential true output 0" }, { "number": "K1", "name": "CLKOUT0N", "type": "Output", "function": "Differential complement output 0" }, { "number": "L1", "name": "CLKOUT1P", "type": "Output", "function": "Differential true output 1" }, { "number": "M1", "name": "CLKOUT1N", "type": "Output", "function": "Differential complement output 1" }, { "number": "M2", "name": "CLKOUT2P", "type": "Output", "function": "Differential true output 2" }, { "number": "M3", "name": "CLKOUT2N", "type": "Output", "function": "Differential complement output 2" }, { "number": "M4", "name": "CLKOUT3P", "type": "Output", "function": "Differential true output 3" }, { "number": "M5", "name": "CLKOUT3N", "type": "Output", "function": "Differential complement output 3" }, { "number": "M6", "name": "CKPWRGD_PDN", "type": "Input", "function": "Power good/Power‑down control" }, { "number": "M7", "name": "CLKOUT4P", "type": "Output", "function": "Differential true output 4" }, { "number": "M8", "name": "CLKOUT4N", "type": "Output", "function": "Differential complement output 4" }, { "number": "M9", "name": "CLKOUT5P", "type": "Output", "function": "Differential true output 5" }, { "number": "M10", "name": "CLKOUT5N", "type": "Output", "function": "Differential complement output 5" }, { "number": "L8", "name": "OEb5/DATA", "type": "Input", "function": "OE for pair 5 (OE mode) / DATA (SBI)" }, { "number": "M11", "name": "CLKOUT6P", "type": "Output", "function": "Differential true output 6" }, { "number": "M12", "name": "CLKOUT6N", "type": "Output", "function": "Differential complement output 6" }, { "number": "L10", "name": "OEb6/CLK", "type": "Input", "function": "OE for pair 6 (OE mode) / CLK (SBI)" }, { "number": "L12", "name": "CLKOUT7P", "type": "Output", "function": "Differential true output 7" }, { "number": "K12", "name": "CLKOUT7N", "type": "Output", "function": "Differential complement output 7" }, { "number": "K11", "name": "OEb7", "type": "Input", "function": "Active‑low OE for pair 7" }, { "number": "J12", "name": "CLKOUT8P", "type": "Output", "function": "Differential true output 8" }, { "number": "H12", "name": "CLKOUT8N", "type": "Output", "function": "Differential complement output 8" }, { "number": "H11", "name": "OEb8", "type": "Input", "function": "Active‑low OE for pair 8" }, { "number": "G12", "name": "CLKOUT9P", "type": "Output", "function": "Differential true output 9" }, { "number": "F12", "name": "CLKOUT9N", "type": "Output", "function": "Differential complement output 9" }, { "number": "E12", "name": "OEb9", "type": "Input", "function": "Active‑low OE for pair 9" }, { "number": "D12", "name": "CLKOUT10P", "type": "Output", "function": "Differential true output 10" }, { "number": "C12", "name": "CLKOUT10N", "type": "Output", "function": "Differential complement output 10" }, { "number": "E11", "name": "OEb10/SHFT_LDN", "type": "Input", "function": "OE for pair 10 (OE mode) / SHFT_LDN (SBI)" }, { "number": "B12", "name": "CLKOUT11P", "type": "Output", "function": "Differential true output 11" }, { "number": "A12", "name": "CLKOUT11N", "type": "Output", "function": "Differential complement output 11" }, { "number": "C11", "name": "OEb11", "type": "Input", "function": "Active‑low OE for pair 11" }, { "number": "A11", "name": "CLKOUT12P", "type": "Output", "function": "Differential true output 12" }, { "number": "A10", "name": "CLKOUT12N", "type": "Output", "function": "Differential complement output 12" }, { "number": "B10", "name": "OEb12", "type": "Input", "function": "Active‑low OE for pair 12" }, { "number": "A9", "name": "CLKOUT13P", "type": "Output", "function": "Differential true output 13" }, { "number": "A8", "name": "CLKOUT13N", "type": "Output", "function": "Differential complement output 13" }, { "number": "A7", "name": "CLKOUT14P", "type": "Output", "function": "Differential true output 14" }, { "number": "A6", "name": "CLKOUT14N", "type": "Output", "function": "Differential complement output 14" }, { "number": "A5", "name": "CLKOUT15P", "type": "Output", "function": "Differential true output 15" }, { "number": "A4", "name": "CLKOUT15N", "type": "Output", "function": "Differential complement output 15" }, { "number": "A3", "name": "CLKOUT16P", "type": "Output", "function": "Differential true output 16" }, { "number": "A2", "name": "CLKOUT16N", "type": "Output", "function": "Differential complement output 16" }, { "number": "A1", "name": "CLKOUT17P", "type": "Output", "function": "Differential true output 17" }, { "number": "B1", "name": "CLKOUT17N", "type": "Output", "function": "Differential complement output 17" }, { "number": "C1", "name": "CLKOUT18P", "type": "Output", "function": "Differential true output 18" }, { "number": "D1", "name": "CLKOUT18N", "type": "Output", "function": "Differential complement output 18" }, { "number": "E1", "name": "CLKOUT19P", "type": "Output", "function": "Differential true output 19" }, { "number": "F1", "name": "CLKOUT19N", "type": "Output", "function": "Differential complement output 19" }, { "number": "EPAD", "name": "EPAD", "type": "Ground", "function": "Exposed pad ground" } ] } ] }