The SiT95315 offers programmable quad fractional frequency translation based jitter cleaning with flexible input to output frequency translation options. The high performance DPLLs support up to 4 differential or 8 single-ended input clocks and provide 12 clock outputs. The clock outputs can be derived from any of the 4 PLLs in a fully flexible manner. This device is fully programmable with the I2C/SPI interface or an on-chip one time (OTP) programmable non-volatile memory for factory pre-programmed devices.
Don’t waste time shipping samples. Request demo & test parts remotely in our lab and qualify for your design today.
We are ready to help you!
Please complete the form below and someone will contact you. Items notated with an * are required.
| "Specs" | "Value" |
|---|---|
| Operating Temperature Range (°C) | -40 to 85 |
| Package Type (mm²) | 9x9 mm, 64-pin QFN |
| Number of Inputs | 4 |
| Number of Outputs | 12 |
| Input Type | LVCMOS, LVDS, LVPECL, CML |
| Input Frequency Range | 8 kHz to 2.1 GHz (Differential) |
| Output Type | LVPECL, CML, HCSL, LVDS, LVCMOS |
| Output Frequency Range | 0.5 Hz to 2.94912 GHz (Differential) |
| Number of PLL/Clock Domains | 4 PLL |
| Phase Jitter (rms) | 85 fs typ.; 70 fs typ. (with MEMS oscillator) |
| Repeatable Input-Output Delay | ±225 ps |
| Frequency Control DCO | 0.001 ppt (all outputs) |
| Phase Control DCO | <1 ps (all outputs) |
| Internal ZDB Mode | <0.5 ns input to output delay variation |
| Programmability | NVM OTP, External EEPROM, Partial autonomous, SPI/I2C |
| Features | Wander attenuation loop bandwidth down to 0.09 mHz, ±25 ps maximum phase hit, JESD204B/C support |
| Availability | Production |
-
64-pin 9x9 mm QFN Clock Generators - Network Synchronizers - Jitter Cleaners package
- Best-in-class 85 fs / 70 fs integrated jitter for quad PLL
- JESD204B/C support for data converter clocks
- Best-in-class hitless switching performance with <25 ps hit
- External EEPROM support and on-chip OTP
- Frequency DCO (0.001 ppt) and phase control DCOs (< 1 ps resolution)
- Internal ZDB on all PLLs with < +/- 500 ps input to output delay across temp
- Independent VDDO (3.3 / 2.5 / 1.8 V)
- Fully flexible output and input mux
- Ethernet
- Optical Transport Network (OTN) Clocking for Framers, Mappers & Processors
- Microwave Backhaul
- 100G / 200G / 400G / 800G Ethernet
- Wireless Networks
- Small Cells
- Storage, Servers & Datacenters
- SONET/SDH Stratum 3
- Test & Measurement
- Broadcast Video
SiT9531x Evaluation Board HW User Manual – Configure and evaluate device performance
Setup SiTGUI SiT953xx 3.6.1.1 – Download software .exe file
| Resource Name | Resource Type | Date | Format | Size |
|---|