Optimize Clock Performance in the Presence of Power Supply Noise
Power supply noise poses a significant challenge to electronic system design. To optimize system performance, engineers must ensure that clocks are resilient to power supply noise. This noise can couple through a clock or timing device to appear as jitter on an output clock.
These two practical strategies can mitigate the effects of power supply noise to maintain optimal system clock performance.
Two Methods for Power Supply Noise Reduction
1. Add sufficient bypass capacitors to power pins.
In the following example, a differential oscillator clocks a high-speed 100 GbE PHY, but the oscillator exhibits higher-than-expected phase-noise spurs in the 100 kHz to 1 MHz range. This is caused by excessive noise on the reference clock’s power (VDD) pin.
The simulated power supply waveform above demonstrates the impact of improper use of a bypass capacitor. With no bypass capacitor the supply noise is 90 mV peak to peak. Placing a low Equivalent Series Resistance (ESR) capacitor (0.1µF–1µF) near the VDD pin minimizes high-frequency noise. In this case, power supply noise was reduced from 90 mV peak to peak to 20 mV peak-to-peak ripple. This illustrates the importance of using low ESR capacitors and strategic placement that is very close to the oscillator VDD pin to mitigate noise effectively. Additionally, a bulk capacitor (~10µF) placed a few millimeters away suppresses low-frequency noise for precision clock sources such as temperature-compensated oscillators (TCXOs) and oven-controlled oscillators (OCXOs), ensuring optimal stability in noisy environments.
2. Choose appropriate inductive elements for power supply LC filters, rated for the device current.
An incorrect choice of the inductive element in a power supply inductor-capacitor (LC) filter can not only impact performance, but it can also cause permanent damage to timing devices. A CMOS device power supply has a maximum rating of 4V, so it’s important to choose the appropriate ferrite bead low-pass filter to suppress resonance peaking and transient overshoot.
The following simulation demonstrates a circuit with an actual model of a ferrite bead, bypass capacitor parasitic and transmission line characteristics. It demonstrates how an incorrect bead—such as one for high-current applications—can deliver an unfavorable frequency response. This example uses a 600 ohm ferrite bead at 100 MHz and reached ~9dB peaking at around 25 kHz. Because of the transient overshoot response, the power supply of the timing device will have a voltage at ~4V. On power up, depending on the supply ramp rate, the LC circuit can cause an overshoot of up to 5.1V, damaging the oscillator.
Using a low-power signal/power supply ferrite-bead, 120 ohm at 100 MHz, reduced LC peaking from 9dB to 1.4dB at ~50kHz. LC transient overshoot reduced from 5.1 to 3.8V with power supply rise time of 5
Managing Power Supply Noise for Optimal System Performance
Managing power supply noise is essential for the optimal function of system clocks. Employing low ESR capacitors, strategically choosing the ferrite bead in LC filters, and ensuring proper component placement are key techniques to mitigate noise and maintain timing component integrity and reliability. By understanding the dynamics of power supply noise and implementing these noise mitigating solutions correctly, engineers can enhance the performance and dependability of electronic systems, ensuring they meet necessary standards and function as intended.
Learn more timing essentials in Common Timing Issues and Solutions.