Hot Chips Paper in IEEE Micro
Posted By: Aaron Partridge

A few days ago the March/April IEEE Micro magazine arrived at my desk. This issue is dedicated to a few selected papers from last summer’s Hot Chips meeting. Out of 75 submissions to Hot Chips, 27 were accepted for oral presentations, and then only 7 of those were selected for publication in IEEE Micro. These papers are all excellent, and one of them is written by Dr. Sassan Tabatabaei of SiTime.It is posted here on SiTime's web site.

High speed digital systems particularly benefit from SiTime’s MEMS-based silicon oscillators. One can divide digital applications into three types: (1) state machines, (2) serial and parallel interfaces that include a clock, and (3) serial interfaces that embed the clock with the data. To be brief I will address only the state machine case, which includes microprocessors and FPGAs.

The ideal reference clock for a state machine must be high frequency and have particularly low jitter. High reference clock frequencies are beneficial for state machines because they  simplify the work of their internal PLLs.All fast state machines rely on internal PLLs to multiply their reference clocks to their internal clock rates and produce the various phases and clock domains used to sequence their computations and data flow (for example at 2.345 GHz). The first problem they have is they must usually multiply up rather low reference frequencies (like 27 MHz) to their multi-GHz internal frequencies. The greater the multiplication, the worse the clock jitter. And to make it more difficult, in order to match external data requirements they must often multiply by highly non-integer values (2345/27 = 86.8519 in the example) which requires pre-dividers that reduce clock quality further. Finally, these PLLs are analog components that must work in very noisy and harsh environments.This all produces poor internal clocks that reduce timing margins and close data eyes.

By providing higher clock frequencies we simplify the task for these PLLs. Less multiplication gives less clock jitter. If special output frequencies are needed then SiTime’s clocks can readily be programmed to deliver integer divisions of those frequencies (for example 234.5 MHz), so the state machine’s PLLs have an easy integer job (in the example just 10x) and no pre-divides. Before SiTime one could not readily do this – most high frequency oscillators were SAW or overtone devices, and you couldn't just order them up in any frequencies you wanted.The result with SiTime oscillators – one gets a lower jitter internal clock with improved timing margin and wider data eyes.

This is a very big deal for cutting-edge digital applications. An executive with a very high-end FPGA company came to me after our Hot Chips talk and said, “Thank you, you are giving us improved timing margin and we are going to suggest our customers use your oscillators.”  Think about that! This company makes some of the world’s fastest chips and their preferred clocks are from SiTime.

Learn more about SiTime’s Oscillators


Feb 11, 2022

Jan 11, 2022