The SiT95145 is a single-chip MEMS jitter cleaner that provides the highest level of clock tree integration and consolidates multiple clock ICs and oscillators into a single device. Its low noise quad-PLL architecture and programmable output drivers provide up to 10 differential or 20 LVCMOS low-jitter clock outputs. It supports 4 additional clock inputs with Frac-N dividers, enabling virtually any input-to-output frequency translation configurations from 8 kHz to 2.1 GHz.
This jitter cleaner integrates SiTime’s third-generation MEMS resonator. This integrated MEMS approach eliminates the dependency on a crystal reference, along with all quartz related issues. It enables a true clock-system-on-a-chip that improves system robustness:
The SiT95145 is supported by TimeMaster™ software to simplify clock tree design. The device can also be shipped with a user-specified, factory pre-programmed default startup configuration. The device configuration can be re-programmed twice using two banks of one-time-programmable (OTP) memory during manufacturing or configured in-system via I2C/SPI for additional BOM flexibility. The SiT95145 is also supported with the SiT6503EB evaluation board.
|Number of Inputs||4|
|Number of Outputs||10|
|Input Frequency Range||8 kHz to 2.1 GHz (differential), 8 kHz to 250 MHz (LVCMOS|
|Output Type||LVPECL, CML, HCSL, LVDS, LVCMOS|
|Output Frequency Range||8 kHz to 2.1 GHz (differential), 8 kHz to 250 MHz (LVCMOS), 1 PPS (one output only)|
|Number of PLL/Clock Domains||4 PLL, 1 time domain|
|Operating Temperature Range (°C)||-40 to +85|
|Phase Jitter (rms)||120 fs|
|Voltage Supply (V)||1.8, 2.5, 3.3|
|Operating Mode||Free running, synchronized, holdover|
|Package Type (mm²)||9x9 mm, 64-pin|
|Features||Hitless switching, zero-delay buffer mode, DCO with 50-ppt resolution, programmable output delay control|
Image: SiT95141 clock generator package 10-output package, top & bottom