SiTime, Silicon MEMS Oscillators and Clock Generators

SiTime's MEMS Timing Packages

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Unlike quartz-based timing products, silicon MEMS devices don’t require special packages that are expensive and bulky. SiTime's MEMS resonators and oscillator ICs are housed together in cost-effective standard plastic packages. With QFN packages that are footprint compatible to quartz devices, SiTime oscillators are drop-in replacements of quartz.

SilTime's all-silicon MEMS devices allow use of modern packaging technologies that offer several benefits.

  • Higher reliability and lower cost
  • Supply chain flexibility
  • MSL-1 rated for long shelf life


SiTime Packages

 
Oscillator Type / Package Footprint (mm x mm)
  QFN
7.0x5.0
QFN
5.0x3.2
QFN
3.5x3.0
QFN
3.2x2.5
QFN
2.5x2.0
QFN
2.0x1.6
SOT23-5
2.9x2.8
DFN
2.0x1.2
CSP
1.5x0.8
Single-ended Oscillators
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Single-ended XT
(eXtremely Thin) Oscillator
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32 kHz Oscillators
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Differential Oscillators
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Clock Generators
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Drop-in Replacements for Quartz

SiTime offers a variety of industry-standard packages that enable 100% drop-in replacement of quartz devices. Because these devices are pin compatible and fit onto common quartz oscillator PCB pad layouts, board design changes are not required to upgrade from quartz to MEMS devices.

Higher Board-level Reliability

SiTime offers SOT23-5 packages for applications that require higher solder joint reliability. These ultra-low-cost leaded packages also offer the benefits of lower-cost optical-only (no X-ray) solder joint inspection and easier re-work capability.

Smallest Oscillator Package

To support space requirements of ultra-small applications, SiTime's 32 kHz oscillators are available in tiny 1.5 x 0.8 x 0.6H mm CSP (chip-scale packages). These 32 kHz devices are the world's smallest oscillators and the first available in CSP.

Lower-profile Packages

MEMS resonators are thinner than any packaged quartz crystal allowing SiTime to manufacture very thin oscillators. Standard packages are 0.75 to 0.90 mm thick, depending on the footprint size. The 3.5 x 3.0 mm XT package is only 0.25 mm high (the same as three sheets of paper) and is the world’s thinnest precision oscillator.

Plastic Packaging

SiTime MEMS resonators and the companion oscillator ICs are molded into plastic packages. SiTime uses low cost plastic injection molded packages for higher reliability, lower lead inductance and improved thermal performance. All SiTime packages are 100% RoHS compliant, lead-free, and are Moisture Sensitivity Level 1 (MSL-1) rated to allow for indefinite storage without drying or special environmental restrictions.

SiTime uses industry-standard plastic packages that are widely used throughout the electronics industry and are available from numerous suppliers. In contrast, quartz device makers use expensive specialized ceramic or metal vacuum packages that are only available from a few suppliers, potentially causing supply chain issues.


Standard Semiconductor Packaging Processes

QFN-packaging-flowMEMS-based timing devices follow a standard semiconductor packaging flow. SiTime’s silicon MEMS resonators are vacuum sealed using an advanced Epi-Seal™ process, which eliminates foreign particles, improves reliability, and enables use of modern packaging technologies.

The packaging flow shown on the left represents the process used for SiTime’s MHz oscillators packaged in quad flat no-lead (QFN) packages. After dicing, MEMS and CMOS chips are mounted, typically in a stacked die arrangement, on lead frame strips or substrates either by flip chip or standard die attach. They are wire bonded with thin gold or copper wires. The populated lead frames or substrates are then transfer molded. The molded devices are singulated and tested on standard handling and automated test equipment.






CSP-packaging-flowThe second flow shows the process for packaging ultra-small 32 kHz oscillators in wafer-level chip scale packages (WLCSP). The MEMS and CMOS wafers are bumped at wafer-scale in a standard chip scale assembly line. The MEMS die are diced and flip-chipped to the CMOS wafer and then epoxy under-fill is applied to the flip-chip interface. The two-die WLCSP wafer is then tested at wafer scale using standard automated test equipment and put into tape and reel after singulation.