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SiTime, Silicon MEMS Oscillators and Clock Generators

Frequently Asked Questions

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Cross Reference and Second Source Parts


Quality and Reliability

Resiliency


µPower Oscillators


High-speed Serial Interfaces and Jitter


Power Consumption


Programmable Features

 

EMI Reduction

Power Supply Noise Suppression

Driving Multiple Loads

 


 


Cross Reference and Second Source Parts


Do you have a cross to quartz oscillators?

Yes. Please contact your local sales representative specifying the part number of the quartz XO including preferred package, operating temperature range and VDD.

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I’ve already designed in a SiLabs MEMS oscillator in my application and need to find a second source. Can you recommend an equivalent footprint compatible part?

The equivalent SiTime families SiT1602 and SiT800x can replace all SiLlabs CMEMS oscillators. Datasheets for this familes can be found here.

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I’ve already designed in a Discera MEMS oscillator in my application and need to find a second source. Can you recommend an equivalent footprint compatible part?

All Discera single-ended (SE) oscillators can be replaced by SiTime SE equivalent parts listed here.
All Discera differential-ended (DE) oscillators can be replaced by SiTime DE equivalent parts listed here.

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Quality and Reliability

 

Are SiTime products RoHS certified?

Yes. All SiTime products are RoHS certified.

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Where can I locate RoHS documents for SiTime products?

Please visit the quality and reliability section of the website. You will need to be a registered user to download documents from this section.

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Are SiTime MEMS-based oscillators subject to "activity dip" issues?

No, they are not.

"Activity dips" are defined as abrupt changes of frequency in a quartz crystal-based oscillator. A crystal-based oscillator may often exhibit an activity dip at critical temperatures, and return just as abruptly to normal behavior for small deviations of temperature away from the critical value.

The most common causes of activity dips are:

  1. "Coupled modes" – the collision of different crystal oscillation modes with different temperature coefficients.
  2. Moisture inside the crystal package condensing onto the quartz plate.

All of these effects can rob the main oscillation mode of energy, effectively causing the crystal to drop out of oscillation or to oscillate temporarily in a different crystal mode.

SiTime MEMS-based oscillators are not subject to these effects for two reasons:

  1. SiTime MEMS oscillation modes are primarily determined by the material properties of silicon; all modes or spurious response characteristics change with temperature in exactly the same manner as the fundamental oscillation mode. Therefore, different modes can never interact at the same frequency and cause a dip.
  2. SiTime's MEMS First™ process uses standard silicon fabrication techniques to hermetically seal the MEMS in a very high-temperature, clean, vacuum environment. This creates an extremely clean, moisture-free environment for the MEMS, and eliminates the possibility of contaminant- or moisture-induced activity dips.

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What are SiTime’s metrics for reliability and quality?

SiTime uses industry standard processes to conduct reliability qualifications of products using accelerated life cycle stress tests like HTOL.

The key reliability metric SiTime publishes is the FIT or (Failure in Time) which provides an estimate of the expected number of device failures after 1 billion hours of operation. A related metric is MTBF (Mean Time between Failure) which is the inverse of FIT.

Other reliability metrics are :
EFR – Early Failure Results
ESD – Electrostatic discharge
LU – Latch-up
MS – Mechanical Shock
VFV – Variable Frequency Vibration
VF – Vibration Fatigue
CA – Constant Acceleration

All SiTime products are designed and brought into production using our robust 6-Sigma processes. Products are fully characterized and qualified per appropriate JEDEC and AEC standards. To ensure the highest quality, SiTime performs Lot Acceptance Testing (LAT) over the temperature range on a sample of parts from each production lot.
SiTime's extremely high quality has been proven over shipment of hundreds of millions of units. Our actual field returns rate is less than 2 DPPM, which is amongst the best in the semiconductor industry. After more than six years of shipments, SiTime has had zero MEMS field failures.

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Why do you publish different FIT values for different products?

FIT (Failure in Time) is a statistically extrapolated value based on accelerated testing (JEDEC22-A108) and applying acceleration factors based on failure modes on the tested devices. The difference in FIT rate across various products is due to different number of devices hours each product was stress tested to.  The FIT numbers are reported when the reliability report is generated. Please refer to the latest reliability reports for the latest FIT values. http://www.sitime.com/support/quality-and-reliability#magictabs_eDH8P_3.

All SiTime products share the same underlying technology and process. As of October 2015, SiTime stress tested thousands of oscillators for a cumulative test time of 3,307,000 device hours with no failures, resulting in a computed FIT value of 0.88 or a MTBF of 1,140 million hours.

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What is the activation energy of MEMS oscillators?

SiTime MEMS oscillators are built with a MEMS resonator and CMOS die using standard semiconductor packaging processes. Since there has been no MEMS resonator failures among the > 250 million products shipped to date, we cannot compute the Activation Energy (Ea) for MEMS. Hence we use the industry standard Ea = 0.7 eV for CMOS as the Ea for the product. We are using the Ea of the worst case element of the device as the Ea for computing the reliability metric, FIT and MTBF for our products. For more details on how we compute the FIT/MTBF values please refer to application note Reliability Calculations for SiTime Oscillators.

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How effective is the hermetic seal of MEMS oscillators?

One of the key elements enabling extremely stable MEMS resonators is SiTime’s Epi-Seal™ process which hermetically seals the resonators during wafer processing, eliminating any need for hermetically sealed packaging. SiTime resonator Epi-Seal is impervious to the highest concentration elements in the atmosphere, nitrogen and oxygen, and therefore acts as a perfect seal. The atmosphere also includes trace amounts of sub-atomic gases: helium at 5.24 part-per-million by volume (ppmv) and hydrogen at 0.55 ppmv concentrations. These gases can diffuse through the Epi-Seal layer and enter the MEMS resonator cavity, resulting in increased pressure. This pressure eventually will equalize with ambient pressure of those gases. Helium leak testing is often used to test hermetically-sealed ceramic packages, including packages used with quartz oscillators. However, it is not relevant to conduct helium leak testing of the SiTime resonator seal quality because the Epi-Seal is not designed to seal against mono-atomic gasses: He and H2.  Such gasses have extremely low concentration in a normal ambient operating environment and have no detrimental operational impact to SiTime resonators in any application. 

For more information on the manufacturing process of MEMS resonators, see our technology paper SiTime's MEMS First™ Process.

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Resiliency


How resilient are SiTime MEMS oscillators against EMI?

SiTime MEMS oscillators are designed to achieve best-in-class resiliency to EMI. The industry standard measurements and performance plots for EMI susceptibility (EMS) are documented in the application note Electromagnetic Susceptibility Comparison of MEMS and Quartz-based Oscillators.

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How resilient are SiTime MEMS oscillators against shock and vibration?

SiTime MEMS oscillators are designed to be less vibration sensitive and extremely shock resistant than similar quartz parts. They are designed to exhibit best-in-class resiliency to shock and vibration, and the industry standard measurements and performance plots for shock and vibration are documented in application note Shock and Vibration Comparison of MEMS and Quartz-based Oscillators.

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What is the PSNR metric of > 1 MHz oscillators?

Power Supply Noise Sensitivity (PSNR) for MHz oscillators is quantified in terms of the amount of jitter induced per mV of power supply noise injected at the specified noise frequency. SiTime MEMS MHz oscillators are designed to achieve best-in-class PSNR performance of 0.5 ps integrated phase Jitter (12 kHz to 20 MHz) per mV of injected power supply noise across frequencies of 10 kHz to 20 MHz.

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What is the PSNR metric of < 1 MHz oscillators?

Power Supply Noise Sensitivity (PSNR) for kHz oscillator families (SiT153x, SiT1552, SiT1630) is quantified in terms of frequency deviation with 300mV peak-to-peak sinusoidal noise injection across frequency range of 10 KHz to 10 MHz. The PSNR plot for the above oscillator familes is provided in the individual datasheets.

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µPower Oscillators


What special considerations are there for measuring frequency of the SiT15xx KHz oscillators?

SiTime recommends using 100 ms or larger gate time with high-resolution frequency counters like the Agilent 53131/2A and Agilent 53230A. For precise frequency measurements of the SiT15xx family of micro-power 32 kHz oscillators, the frequency counter must have either a high stability OCXO reference or be disciplined by GPS or Rubidium clock reference. For other instruments, like time interval analyzers or simple counters, a gate time of 1 sec or higher is recommended. For details refer to application note Measurement Guidelines for 32kHz SiT15xx Oscillators.

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What special considerations are there for measuring IDD of Si15xx KHz products?

Typical no load operating supply current of a SiT15xx device is around 850 nA at room temperature depending on the voltage swing of the output stage. When measuring supply current down to the nano-amp range, a high-resolution digital ammeter similar to an Agilent 34401A must be used.  For details refer to the application note Measurement Guidelines for 32kHz SiT15xx Oscillators.

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What are the layout recommendations and manufacturing guidelines for CSP packages?

The layout recommendations for the CSP package can be found in the application note Best Design and Layout Practices
The manufacturing guidelines are listed on page 10 of the SiT1532 data sheet.

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What are the layout recommendations and manufacturing guidelines for 2.0 mm x 1.2 mm packages?

The layout recommendations for the 2012 package can be found in the application note Best Design and Layout Practices
The manufacturing guidelines are listed on page 9 of the SiT1533 datasheet.

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High-speed Serial Interfaces and Jitter

 

What part numbers or product families do you recommend for various serial interfaces including USB, PCIe, Ethernet or Fibre Channel?

Our ultra-performance single-ended SiT820x families and differential-ended SiT912x families offer the best jitter margin as reference clocks for the following serial interfaces.

  • USB 2.0
  • PCIe 1.0, PCIe 2.0, PCIe 3.0
  • SAT-2, SAT-3
  • SAS, SAS-2, SAS-3
  • 1, 10 and 40 GbE
  • 1GFC, 2GFC, 4GFC

For applications that are power sensitive, our low power single-ended oscillator families SiT1602, SiT8008/9, SiT1618, SiT891x, SiT892x are recommended for the following interfaces.

  • USB 2.0
  • SAT-2, SAT-3
  • SAS, SAS-2, SAS-3
  • EPON
  • 1 GbE

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How do I get C2C specs for your non spread-spectrum clocks?

Peak-to-peak cycle-to-cycle jitter (C2C) can be calculated from the period jitter (PerJ) spec specified in the datasheet as follows.
C2C_rms =faq-latest_clip_image002 * PerJ_rms
C2C_p-p = 2 * 3.09 * C2C_rms, for 1000 samples

For example: peak-to-peak C2C jitter for SiT9120 would be 12.8 ps p-p typical and 18.2 ps p-p max.

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The datasheets specify period and phase jitter at a specific frequency.  Where can I find respective jitter numbers for other frequencies I'm using in my application?

SiTime datasheets for the individual oscillator families specify jitter at a particular VDD and output frequency. All SiTime devices within the same family will exhibit similar period and phase jitter across all supported frequencies under the same VDD condition. Period and phase jitter values are also provided in performance reports.  These reports are accessible to registered users of the SiTime web site.

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How do I access phase noise plots?

Phase noise plots are included in SiTime’s performance reportshttp://www.sitime.com/support/performance-measurement-report. These reports are accessible to registered users of the SiTime web site.

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How do I get phase noise plots or tables for a specific frequency not found in your performance reports?

Contact your local SiTime sales representative http://www.sitime.com/sales/reps-and-distributors and  specify the following.

  • Base family part number (SiT1602, SiT820x, etc.)
  • Nominal frequency in Hz
  • VDD (1.8/2.5/3.3) in volts
  • Start frequency offset (10, 100, 1K) in Hz

For a quick estimate, use the following equation to derive the phase noise for your specific frequency:

   PNs = PNi +  20*Log (Fs/Fi)

Where;
Fi       –  Nominal frequency of published phase noise
Fs      –  Nominal frequency for which phase noise is requested
PNi    –  Published phase noise

PNs   –  Derived phase noise for specific nominal frequency

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Power Consumption

 

How does the load affect current consumption?

In most applications, the LVCMOS oscillator drives capacitive loads. During the rising edges, the device draws current from the power supply to charge up load capacitance. During the falling edges, the capacitance discharges to GND. The average current going through the load depends on the following parameters:

Output frequency (Fout). This determines how often current is drawn from the power supply.

  1. Load capacitance value (Cload). Larger capacitance values require more current to charge up load capacitance.
  2. Power supply voltage (Vdd). More current is required to charge up the load to higher voltages.

The additional power supply current from the load is computed as below:

I_load = Cload * Vdd * Fout

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The datasheets for LVCMOS oscillators provide IDD at specific frequencies. How do I estimate IDD at other frequencies?

The no load current consumption for output frequency at F1 can be estimated as a sum of (1) no load current at reference frequency F0, which is specified in the datasheet, and (2) the difference in drive current on internal capacitance between two frequencies, as per the equation below:
equation-power

Where:
IDD_NL_F1 : No load current consumption at frequency F1,
IDD_NL_F0 : No load current consumption specified in datasheet at frequency F0,
VDD : Power supply voltage,
CINT : Internal capacitance is:
   6.5 pF (typ.) and 8 pF (max.) for SiT1602, SiT8008/9, SiT1618, SiT8918/9, SiT8920/1/4/5 families
   12 pF (typ.) and 14 pF (max.) for SiT8208/9, SiT8225, SiT8256, SiT3807/8/9,SiT3701, SiT8102 families

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What is the output impedance of SiTime LVCMOS clocks?

See table in Appendix C of the application note on Termination Recommendations for Single-ended Oscillator Driving Single or Multiple Loads.

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Programmable Features

 

Are SiTime oscillators programmable?

Yes. SiTime oscillators are designed with a programmable architecture that enables configuration of several parameters including any output frequency (to six decimals of accuracy), frequency stability (ppm), and supply voltage within the device’s operating range. Additional features such as drive strength can be programmed and functionality of pin 1 can be changed to match application requirements. See the Ordering Information page within product datasheets for details on specification options or our website for an overview on available features.

Depending upon quantity and lead-time requirements, SiTime oscillators can be programmed at the factory for production volumes (three to five week lead times), programmed by specific authorized distributors (24 hour lead times), or instantly programmed in the field using a Time Machine II portable programmer for sample volumes.

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What is the difference between the OE and ST features?

The feature pin for most SiTime oscillators (pin 1) can be programmed to either "output enable" (OE) or "standby" (ST) functions. In both cases, pulling pin 1 Low stops the device's output oscillation, but in two different ways, as described below.

Applying logic Low to the OE pin only disables the output driver and puts it in Hi-Z mode, but the rest of the device is still running. Power consumption decreases due to the inactivity of the output. For example, for a 3.3V SiT8003 20 MHz device, the IDD decreases from 4 mA to 3.3 mA for a 15 pF load. When the OE pin is pulled High, the output typically enables in less than 1 us.

A device with an ST pin enters standby mode when the ST pin is pulled Low. All internal circuits of the device turn off and the current is reduced to a standby current, typically in the range of a few microAmps. When ST is pulled High, the device goes through the "resume" process, which can take from 3 ms to 10 ms. The standby current and resume time period are specified in the device datasheets. Some SiTime datasheets do not specify the resume time specifically; in those cases, the resume time is the same as the "start-up time."

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Can I program SiTime devices to drive loads larger than 15 pF?

Yes. SiTime devices with single-ended LVCMOS outputs are generally specified with a 15 pF capacitive load for rise and fall times. The device may drive a larger load, up to 60 pF, with slower rise and fall times. For the applications requiring both fast rise and fall times (~1 ns) and the ability to drive large capacitive loads, buffer devices with high drive strength output are available upon request. Contact SiTime for more details.

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Can I adjust the output rise and fall times of SiTime oscillators?

Yes. Users may adjust the output buffers of SiTime oscillator by changing the drive current strength. By increasing or decreasing the maximum drive current of the output stage, rise and fall times may be reduced or increased, respectively. A high drive current strength enables faster rise and fall times while driving a larger load. A low drive current strength reduces the clock edge slew rate and reduces potential EMI. 

SiTime offers field programmable oscillators for use with the Time Machine II, an oscillator programmer that allows users to configure various parameters including rise and fall time.

See SiTime datasheets for more details or contact SiTime for ordering parts with modified drive strength.

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Can I program SiTime oscillators with a lab-based programmer?

Yes. SiTime offers field programmable oscillators for use with the Time Machine™ II, a complete and portable programmer kit. This tool can program the frequency, voltage, stability and other functional characteristics such as drive strength or spread spectrum. The programmer and field programmable devices are ideal for fast prototyping and optimizing system performance by creating instant samples with custom frequencies or adjusting drive strength. The field programmable oscillators have industry-standard footprints so they can be used as drop-in replacements for legacy quartz oscillators without requiring any board changes. See field programmable oscillators and Time Machine II for details.

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Can I program a SiTime oscillator in my system?

SiTime offers the following options for in-system programmability:

  1. For applications that only require two frequencies, SiTime offers the SiT8033 two-frequency programmable oscillator. The output of this device can be switched between two frequencies in a user system via a logic-level signal. The two frequencies are pre-selected, and are programmed at the factory.
  2. Digitally-controlled oscillators (DCXO) with LVCMOS outputs (SiT3907) and differential outputs (SiT3921 and SiT3922). These oscillators allow users to vary the output frequency dynamically within a narrow range (up to ±1600 ppm) and with very high resolution (1 ppb). These devices also replace the analog interface in many VCXO applications.
  3. Serially programmable frequency select devices (SiT3509). These devices allow users to select nine different, unrelated frequencies by writing to internal device registers through SiTime's 1-wire tri-level interface. This family also includes the SiT3519 DCXO that allows users to dynamically vary the output frequency up to ±1600 ppm. Contact SiTime for more information.

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EMI Reduction

 

Are there any MEMS clocking solutions available that can mitigate EMI issues?

SiTime MEMS oscillators offer two configurable features that address EMI issues for environmental compliance without requiring any modifications to the PCB design.

  1. Programmable Drive Strength
    1. Reducing drive strength increases the rise-fall time of the clock waveform, thereby attenuating the power of EM waves at higher harmonics
    2. The drive strength table in datasheets lists supported drive strengths, achievable rise-fall time for various load capacitances from 5 pf to 60 pf
    3. Effective at mitigating EM sourced from clock trace
  2. Spread Spectrum Clocking
    1. Support for center and down spread achieves up to -17 dB attenuation of 3rd harmonic and higher EM waves
    2. Spread range: ±0.25% to ±2% center and -0.5% to 4% down spread
    3. Effective at mitigating EM at the system level

For more information, see spread spectrum oscillator page or application note SiTime Spread Spectrum Clock Oscillators.

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Most of MCU and FPGA designs are implemented as synchronous digital blocks. The clock tree for these blocks is derived from a common external clock reference. SiTime recommends using down spread clock sources to ensure that the setup and hold times are not violated across process, VDD, and temperature for the critical timing paths in these blocks.

For more information, see spread spectrum oscillator page or application note SiTime Spread Spectrum Clock Oscillators.

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Power Supply Noise Suppression

 

1 MHz oscillators">What are the recommendations for decoupling capacitors for > 1 MHz oscillators?

SiTime recommends a 0.1 uF low ESR multi-layer ceramic chip capacitor placed close to and across the VDD and GND pins for all MHz oscillators.

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What bypass/decoupling do you recommend for the SiT15xx families?

For < 1 MHz oscillator families (SiT153x, SiT1552 or SiT1630) a bypass capacitor is not required. These families have internal bulk filtering that provides sufficient power supply filtering for noise up to 300 mV peak-to-peak and 10 MHz frequency component.

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What are the recommendations for cleaning a noisy power rail?

Both LC and RC filter on VDD can be considered for power supply noise filtering. An LC filter has less voltage drop and is preferred for oscillator families with IDD > 5 mA.  An RC filter can be used for oscillators drawing under 5 mA. More details are provided in application note Best Design and Layout Practices.

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Does the operating supply voltage tolerance specified in the datasheet, e.g. +/-10% of nominal VDD, imply the maximum amplitude of AC ripple noise that the part can tolerate?

No. The operating supply voltage tolerance in the datasheet specifies the DC voltage range to which the device has been characterized. This DC voltage tolerance, typically 10% of nominal VDD, should not be confused with the AC noise ripple on the supply voltage. The capability to reject AC noise from voltage supply is defined by Power Supply Noise Sensitivity (PSNS) which measures the amount of additional jitter induced by the AC noise ripple over a certain power supply noise spectrum range.

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Driving Multiple Loads

 

How does the load affect current consumption?

In most applications, the LVCMOS oscillator drives capacitive loads. During the rising edges, the device draws current from the power supply to charge up load capacitance. During the falling edges, the capacitance discharges to GND. The average current going through the load depends on the following parameters:

Output frequency (Fout). This determines how often current is drawn from the power supply.

  1. Load capacitance value (Cload). Larger capacitance values require more current to charge up load capacitance.
  2. Power supply voltage (Vdd). More current is required to charge up the load to higher voltages.

The additional power supply current from the load is computed as below:

I_load = Cload * Vdd * Fout

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What is the output impedance of SiTime LVCMOS clocks?

See table in Appendix C of the application note on Termination Recommendations for Single-ended Oscillator Driving Single or Multiple Loads.

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Can I program SiTime devices to drive loads larger than 15pF?

Yes. SiTime devices with single-ended LVCMOS outputs are generally specified with a 15 pF capacitive load for rise and fall times. The device may drive a larger load, up to 60 pF, with slower rise and fall times. For the applications requiring both fast rise and fall times (~1 ns) and the ability to drive large capacitive loads, buffer devices with high drive strength output are available upon request. Contact SiTime for more details.

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My application requires the same MHz clock sources at multiple locations. Do you have a clock fan-out buffer?

We don’t offer clock fan out buffers. However, our clock driver can be configured to drive multiple loads. For details, refer to application note Termination Recommendations for Single-ended Oscillator Driving Single or Multiple Loads

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Are there any signal integrity (SI) issues with driving multiple loads at end of long traces with 32 kHz MEMS oscillators?

No. The slew rate of µPower 32 kHz oscillators is in the order of 10s of ns. Hence multiple loads at the end of up to 10” traces can be driven without any concern of signal integrity or reflections. For details, refer to application note Driving Multiple Loads with 32 kHz Nano-Power MEMS Oscillators.

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