SiTime, Silicon MEMS Oscillators and Clock Generators

CMOS Digital Design Principal Engineer / Manager

E-mail Print

The CMOS Digital Design Principal Engineer / Manager is a hands-on role, contributing to building precision timing circuits, leveraging SiTime’s industry-leading MEMS technology, that span high-performance Networking and Communications Infrastructure market application requirements and ultra-low power Mobile platforms including wearable devices.

The ideal candidate is a highly motivated, self-starting, Principal Engineer or hands-on first-level Manager adept at executing Digital Design, Verification and CAD tasks and possessing excellent technical and communications skills to collaborate with Remote Design Centers and Outside Vendors. 

Responsibilities:

  • Contribute to Architectural definition and partitioning of CMOS platform chips
  • Algorithm and Mathematical Function mapping to Digital Logic Designs
  • Logic and State-Machine Design in Verilog
  • Developing Behavioral Models for Analog Blocks
  • Mixed-Model co-simulation of Digital Blocks together with Analog Behavioral Models
  • Block-level Test-Bench generation and verification
  • Top-level chip integration, Test Bench generation and verification
  • Implementing DFT, DFD
  • Test-time and Chip-area optimized high fault coverage implementations
  • Implementing DFM hooks
  • Installation and upkeep of front-end and back-end CAD software licenses
  • Interfacing with 3rd party IP vendors
  • Managing Design Services personnel to address Library Characterization, Place-and-Route, DFT tool deployment , as needed on CMOS platform developments
  • Contribute to the architectural definition of the design, and also to chip integration
  • Collaborate with resources located at Remote Design Centers and Outside Vendors
  • Actively participate in the chip bring up, evaluation and characterization, with emphasis on owned blocks
  • Address questions and issues related to his/her blocks raised by cross-functional personnel, such as Product, Characterization, Test, or Application Engineers

 

Requirements:

A candidate with a demonstrated record of success and who has the following attributes:

  • Passionate, self-starter with strong commitment to flawless execution
  • Strong attention-to-detail, deploying robust design methodology and thorough design reviews
  • Proven track record of designing and producing (in high volume) profitable complex mixed-signal chips
  • Track record of execution from Product Concept through Design Implementation, Tape-out, Sampling and production release
  • 10-plus years of industry experience in Mixed-Mode Digital Design, Verification, Digital Standard Cell Library Characterization, Static Timing Analysis, Test Bench Generation, DFT, and CAD tool deployment
  • 3-plus years proven experience in hands-on design leadership role
  • Excellent Command of programming languages including Verilog, PERL, Skill
  • Excellent written and verbal communications skills
  • Education: BSEE, MSEE preferred